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Results 1 - 4 of 4 for ORR (0.02 sec)

  1. src/cmd/asm/internal/asm/testdata/arm.s

    	ORR	R0->28, R1           // 401e81e1
    	ORR	R0@>28, R1           // 601e81e1
    	ORR.S	R0<<28, R1           // 001e91e1
    	ORR.S	R0>>28, R1           // 201e91e1
    	ORR.S	R0->28, R1           // 401e91e1
    	ORR.S	R0@>28, R1           // 601e91e1
    	ORR	R0<<R1, R2, R3       // 103182e1
    	ORR	R0>>R1, R2, R3       // 303182e1
    	ORR	R0->R1, R2, R3       // 503182e1
    	ORR	R0@>R1, R2, R3       // 703182e1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "ORshiftLL", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64"},                    // arg0 | arg1<<auxInt, auxInt should be in the range 0 to 63.
    		{name: "ORshiftRL", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64"},                    // arg0 | arg1>>auxInt, unsigned shift, auxInt should be in the range 0 to 63.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/arm64.s

    	AND	$(1<<63-1), R1                      // AND	$9223372036854775807, R1        // 21f84092
    	ORR	$(1<<63), R1                        // ORR	$-9223372036854775808, R1       // 210041b2
    	ORR	$(1<<63-1), R1                      // ORR	$9223372036854775807, R1        // 21f840b2
    	EOR	$(1<<63), R1                        // EOR	$-9223372036854775808, R1       // 210041d2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 94.9K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm/asm5.go

    		rt := int(p.To.Reg)
    		if r == 0 {
    			r = rt
    		}
    		x, y := immrot2a(uint32(c.instoffset))
    		var as2 obj.As
    		switch p.As {
    		case AADD, ASUB, AORR, AEOR, ABIC:
    			as2 = p.As // ADD, SUB, ORR, EOR, BIC
    		case ARSB:
    			as2 = AADD // RSB -> RSB/ADD pair
    		case AADC:
    			as2 = AADD // ADC -> ADC/ADD pair
    		case ASBC:
    			as2 = ASUB // SBC -> SBC/SUB pair
    		case ARSC:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 79.4K bytes
    - Viewed (0)
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