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Results 1 - 3 of 3 for Col1 (0.07 sec)

  1. pkg/volume/csi/csi_attacher_test.go

    				{"vol1", volume.NewSpecFromPersistentVolume(makeTestPV("pv1", 20, testDriver, "vol1"), false), true},
    			},
    		},
    		{
    			name: "include non-attable",
    			attachedSpecs: []attachedSpec{
    				{"vol0", volume.NewSpecFromPersistentVolume(makeTestPV("pv0", 10, testDriver, "vol0"), false), true},
    				{"vol1", volume.NewSpecFromVolume(makeTestVol("pv1", testDriver)), false},
    			},
    Registered: Sat Jun 15 01:39:40 UTC 2024
    - Last Modified: Thu Apr 18 12:23:16 UTC 2024
    - 58.1K bytes
    - Viewed (0)
  2. pkg/volume/csi/csi_mounter_test.go

    			mode:   storage.VolumeLifecyclePersistent,
    			fsType: "zfs",
    			spec: func(fsType string, options []string) *volume.Spec {
    				pvSrc := makeTestPV("pv1", 20, testDriver, "vol1")
    				pvSrc.Spec.CSI.FSType = fsType
    				pvSrc.Spec.MountOptions = options
    				return volume.NewSpecFromPersistentVolume(pvSrc, false)
    			},
    		},
    		{
    Registered: Sat Jun 15 01:39:40 UTC 2024
    - Last Modified: Wed Apr 24 18:25:29 UTC 2024
    - 50.1K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/loong64/asm.go

    	case 66: // am* From, To, RegTo2 ==> am* RegTo2, From, To
    		rk := p.From.Reg
    		rj := p.To.Reg
    		rd := p.RegTo2
    
    		// See section 2.2.7.1 of https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html
    		// for the register usage constraints.
    		if rd == rj || rd == rk {
    			c.ctxt.Diag("illegal register combination: %v\n", p)
    		}
    		o1 = OP_RRR(atomicInst[p.As], uint32(rk), uint32(rj), uint32(rd))
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 61.8K bytes
    - Viewed (0)
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