VPSHRDQ $79, Y13, Y20, K2, Y21                     // 62c3dd2273ed4f
	VPSHRDQ $79, Y20, Y20, K2, Y21                     // 62a3dd2273ec4f
	VPSHRDQ $79, (R14), Y20, K2, Y21                   // 62c3dd22732e4f
	VPSHRDQ $79, -7(DI)(R8*8), Y20, K2, Y21            // 62a3dd2273acc7f9ffffff4f
	VPSHRDQ $79, Y24, Y14, K2, Y21                     // 62838d2a73e84f
	VPSHRDQ $79, Y13, Y14, K2, Y21                     // 62c38d2a73ed4f

0000400 e1 42 1b d2 61 d6 79 ec fd 3e 44 28 a4 51 6c 5c
0000410 fc d2 72 ca ba 82 18 46 16 61 cd 93 a9 0f d1 24
0000420 17 99 e2 2c 71 16 84 0c c8 7a 13 0f 9a 5e c5 f0
0000430 79 64 e2 12 4d c8 82 a1 81 19 2d aa 44 6d 87 54
0000440 84 71 c1 f6 d4 ca 25 8c 77 b9 08 c7 c8 5e 10 8a
0000450 8f 61 ed 8c ba 30 1f 79 9a c7 60 34 2b b9 8c f8
0000460 18 a6 83 1b e3 9f ad 79 fe fd 1b 8b f1 fc 41 6f

	POPQ GS  // 0fa9
	// All instructions below semantically have unsigned operands,
	// but previous assembler permitted negative arguments.
	// This behavior is preserved for compatibility reasons.
	VPSHUFD $-79, X7, X7         // c5f970ffb1
	RORXL $-1, (AX), DX          // c4e37bf010ff
	RORXQ $-1, (AX), DX          // c4e3fbf010ff
	VPSHUFD $-1, X1, X2          // c5f970d1ff
	VPSHUFD $-1, Y1, Y2          // c5fd70d1ff