RLWMI $7, R3, $1, R6            // 50663ffe
	RLWMI $7, R3, $2147483648, R6   // 50663800
	RLWMI $7, R3, $65535, R6        // 50663c3e
	RLWMI $7, R3, $16, $31, R6      // 50663c3e
	RLWMICC $7, R3, $65535, R6      // 50663c3f
	RLWMICC $7, R3, $16, $31, R6    // 50663c3f
	RLWNM $3, R4, $7, R6            // 54861f7e
	RLWNM $0, R4, $7, R6            // 5486077e
	RLWNM R0, R4, $7, R6            // 5c86077e

	AND	R1@>33, R2
	AND	$(1<<63), R1                        // AND	$-9223372036854775808, R1       // 21004192
	AND	$(1<<63-1), R1                      // AND	$9223372036854775807, R1        // 21f84092
	ORR	$(1<<63), R1                        // ORR	$-9223372036854775808, R1       // 210041b2
	ORR	$(1<<63-1), R1                      // ORR	$9223372036854775807, R1        // 21f840b2

	ADD	R1@>R2, R3, R4
	ADD	R1->R2, R3, R4
	ADD	R1, R2, R3
	ADD	R(1)<<R(2), R(3), R(4) // ADD	R1<<R2, R3, R4

//	LTYPE1 cond imsr ',' spreg ',' // asm doesn't support trailing comma.
//	{
//		outcode($1, $2, &$3, $5, &nullgen);
//	}
//	LTYPE1 cond imsr ',' reg
//	{
//		outcode($1, $2, &$3, 0, &$5);
//	}
	ADD	$1, R2
	ADD	R1<<R2, R3
	ADD	R1>>R2, R3
	ADD	R1@>R2, R3
	ADD	R1->R2, R3
	ADD	R1, R2

//