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src/cmd/asm/internal/asm/testdata/arm.s
ADD R1@>R2, R3, R4 ADD R1->R2, R3, R4 ADD R1, R2, R3 ADD R(1)<<R(2), R(3), R(4) // ADD R1<<R2, R3, R4 // LTYPE1 cond imsr ',' spreg ',' // asm doesn't support trailing comma. // { // outcode($1, $2, &$3, $5, &nullgen); // } // LTYPE1 cond imsr ',' reg // { // outcode($1, $2, &$3, 0, &$5); // } ADD $1, R2 ADD R1<<R2, R3 ADD R1>>R2, R3 ADD R1@>R2, R3 ADD R1->R2, R3 ADD R1, R2 //
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Click Count (0)