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Results 1 - 8 of 8 for sdiv (0.05 sec)
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src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
{name: "DIV", argLength: 2, reg: gp21, asm: "SDIV"}, // arg0 / arg1, signed {name: "UDIV", argLength: 2, reg: gp21, asm: "UDIV"}, // arg0 / arg1, unsigned
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/asm.go
case AMULHV: return 0x3c << 15 // mulh.d case AMULHVU: return 0x3d << 15 // mulhu.d case ADIV: return 0x40 << 15 // div.w case ADIVU: return 0x42 << 15 // div.wu case ADIVV: return 0x44 << 15 // div.d case ADIVVU: return 0x46 << 15 // div.du case AREM: return 0x41 << 15 // mod.w case AREMU: return 0x43 << 15 // mod.wu case AREMV:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 61.8K bytes - Viewed (0) -
platforms/documentation/docs/src/docs/css/manual.css
.conum:not([data-value]):empty { display: none; } dt, th.tableblock, td.content, div.footnote { text-rendering: optimizeLegibility; } h1, h2, p, td.content, span.alt { letter-spacing: -0.01em; } p strong, td.content strong, div.footnote strong { letter-spacing: -0.005em; } p, blockquote, dt, td.content,
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Sat May 25 05:15:02 UTC 2024 - 72.6K bytes - Viewed (0) -
src/math/big/int_test.go
} if q2.Cmp(q) != 0 || r2.Cmp(r) != 0 { t.Errorf("#%d QuoRem: got (%s, %s), want (%s, %s)", i, q2, r2, q, r) } d1 := new(Int).Div(x, y) m1 := new(Int).Mod(x, y) if !isNormalized(d1) { t.Errorf("#%d Div: %v is not normalized", i, *d1) } if !isNormalized(m1) { t.Errorf("#%d Mod: %v is not normalized", i, *m1) } if d1.Cmp(d) != 0 || m1.Cmp(m) != 0 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 18:42:28 UTC 2024 - 58.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/optimize_patterns.td
def ExpandTo4DForDepthwiseConv: NativeCodeCall< "ExpandTo4DForDepthwiseConv($0)">; // If we see a (div or Mul) op (dividing/multiplying) a constant value // to a convolution op with constant filter and bias, we can fuse the div/mul // into the convolution op by constant folding // the filter/bias and the div/mul op's constant operand. // The following pattern restricts to float constant values for now.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 16 20:31:41 UTC 2024 - 66.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
FMULCC F1, F2, F3 // fc620073 FMULS F1, F2 // ec420072 FMULS F1, F2, F3 // ec620072 FMULSCC F1, F2, F3 // ec620073 FDIV F1, F2 // fc420824 FDIV F1, F2, F3 // fc620824 FDIVCC F1, F2, F3 // fc620825 FDIVS F1, F2 // ec420824 FDIVS F1, F2, F3 // ec620824
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y)) (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y)) (Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...) (Mul(32|64)F ...) => ((FMULS|FMUL) ...) (Div(32|64)F ...) => ((FDIVS|FDIV) ...) // Lowering float <=> int (Cvt32to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD (SignExt32to64 x))) (Cvt64to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD x)) (Cvt32Fto(32|64) x) => (MFVSRD (FCTI(W|D)Z x))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
analysis/analysis-api-fir/src/org/jetbrains/kotlin/analysis/api/fir/components/KaFirResolver.kt
): CompoundArrayAccessPartiallyAppliedSymbols? { // The last argument of `set` is the new value to be set. This value should be a call to the respective `plus`, `minus`, // `times`, `div`, or `rem` function. val operationCall = fir.arguments.lastOrNull() as? FirFunctionCall ?: return null
Registered: Wed Jun 12 09:53:16 UTC 2024 - Last Modified: Tue Jun 11 15:45:42 UTC 2024 - 73K bytes - Viewed (0)