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Results 1 - 10 of 16 for div1 (0.05 sec)
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tensorflow/compiler/jit/deadness_analysis_test.cc
DependentInductionVar div0 = CreateDependentLoopInvariantValue(root, "div0", "loop", iv.loop_cond, 0); DependentInductionVar div1 = CreateDependentLoopInvariantValue(root, "div1", "loop", iv.loop_cond, 0); FixupSourceAndSinkEdges(root.graph()); TF_ASSERT_OK(root.graph()->UpdateEdge(div1.induction_var.node(), 0, div0.latch.output_true.node(), 0));
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Feb 22 06:59:07 UTC 2024 - 51.6K bytes - Viewed (0) -
pkg/kubelet/cm/devicemanager/manager_test.go
constructDevices([]string{"dev1"}), newContainerAllocateResponse( withDevices(map[string]string{"/dev/dev1": "/dev/dev1"}), withMounts(map[string]string{"/home/lib1": "/usr/lib1"}), ), ) testManager.healthyDevices[extendedResourceName] = sets.New[string]() testManager.healthyDevices[extendedResourceName].Insert("dev1") // checkpoint is present, indicating node hasn't been recreated
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Tue Jun 04 06:25:43 UTC 2024 - 65K bytes - Viewed (0) -
subprojects/core/src/integTest/groovy/org/gradle/api/tasks/CopyTaskIntegrationSpec.groovy
} def "copy fails by default when duplicates are present"() { given: file('dir1/path/file.txt').createFile() << 'f1' file('dir2/path/file.txt').createFile() << 'f2' buildScript ''' task copy(type: Copy) { from 'dir1' from 'dir2' into 'dest' } '''.stripIndent()
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Wed Apr 03 15:21:23 UTC 2024 - 67.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Select0 (Mul64uhilo x y)) => (MULHDU x y) (Select1 (Mul64uhilo x y)) => (MULLD x y) (Div64 [false] x y) => (DIVD x y) (Div64u ...) => (DIVDU ...) (Div32 [false] x y) => (DIVW x y) (Div32u ...) => (DIVWU ...) (Div16 [false] x y) => (DIVW (SignExt16to32 x) (SignExt16to32 y)) (Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y)) (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y)) (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
okhttp/src/test/java/okhttp3/internal/cache/DiskLruCacheTest.kt
filesystem.createDirectories(it) } filesystem.write(file) { writeUtf8(content) } } private fun generateSomeGarbageFiles() { val dir1 = cacheDir / "dir1" val dir2 = dir1 / "dir2" writeFile(getCleanFile("g1", 0), "A") writeFile(getCleanFile("g1", 1), "B") writeFile(getCleanFile("g2", 0), "C") writeFile(getCleanFile("g2", 1), "D")
Registered: Sun Jun 16 04:42:17 UTC 2024 - Last Modified: Mon Apr 15 14:55:09 UTC 2024 - 75.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
MULHWUCC R3, R4, R5 // 7ca41817 MULLDV R3, R4, R5 // 7ca41dd2 MULLDVCC R3, R4, R5 // 7ca41dd3 DIVD R3,R4 // 7c841bd2 DIVD R3, R4, R5 // 7ca41bd2 DIVW R3, R4 // 7c841bd6 DIVW R3, R4, R5 // 7ca41bd6 DIVDCC R3,R4, R5 // 7ca41bd3 DIVWCC R3,R4, R5 // 7ca41bd7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
tensorflow/compiler/jit/mark_for_compilation_pass_test.cc
for (Node* n : graph->nodes()) { if (absl::EndsWith(n->name(), /*suffix=*/"dev0")) { n->set_assigned_device_name(string(xla_gpu_dev0)); } else if (absl::EndsWith(n->name(), /*suffix=*/"dev1")) { n->set_assigned_device_name(string(xla_gpu_dev1)); } } TF_ASSERT_OK(MarkForCompilationPassTestHelper::MarkForCompilation(&graph)); // Each of the MatMuls should be in a separate cluster.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Feb 14 10:11:10 UTC 2024 - 79.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390XOps.go
{name: "DIVD", argLength: 2, reg: gp21tmp, asm: "DIVD", resultInArg0: true, clobberFlags: true}, // arg0 / arg1 {name: "DIVW", argLength: 2, reg: gp21tmp, asm: "DIVW", resultInArg0: true, clobberFlags: true}, // arg0 / arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(Div64F ...) => (FDIV ...) (Div64 x y) => (DIVD x y) (Div64u ...) => (DIVDU ...) // DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor, // so a sign/zero extension of the dividend is required. (Div32 x y) => (DIVW (MOVWreg x) y) (Div32u x y) => (DIVWU (MOVWZreg x) y) (Div16 x y) => (DIVW (MOVHreg x) (MOVHreg y)) (Div16u x y) => (DIVWU (MOVHZreg x) (MOVHZreg y)) (Div8 x y) => (DIVW (MOVBreg x) (MOVBreg y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/prove.go
// TODO: add other architectures? if b.Func.Config.arch != "386" && b.Func.Config.arch != "amd64" { break } divr := v.Args[1] divrLim, divrLimok := ft.limits[divr.ID] divd := v.Args[0] divdLim, divdLimok := ft.limits[divd.ID] if (divrLimok && (divrLim.max < -1 || divrLim.min > -1)) || (divdLimok && divdLim.min > mostNegativeDividend[v.Op]) {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:30:21 UTC 2024 - 48.9K bytes - Viewed (0)