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Results 1 - 5 of 5 for DIVD (0.09 sec)
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src/cmd/asm/internal/asm/testdata/ppc64.s
MULLWVCC R3, R4, R5 // 7ca41dd7 MULHWUCC R3, R4, R5 // 7ca41817 MULLDV R3, R4, R5 // 7ca41dd2 MULLDVCC R3, R4, R5 // 7ca41dd3 DIVD R3,R4 // 7c841bd2 DIVD R3, R4, R5 // 7ca41bd2 DIVW R3, R4 // 7c841bd6 DIVW R3, R4, R5 // 7ca41bd6 DIVDCC R3,R4, R5 // 7ca41bd3
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390XOps.go
{name: "MULHDU", argLength: 2, reg: gp21tmp, asm: "MULHDU", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true}, // (arg0 * arg1) >> width {name: "DIVD", argLength: 2, reg: gp21tmp, asm: "DIVD", resultInArg0: true, clobberFlags: true}, // arg0 / arg1 {name: "DIVW", argLength: 2, reg: gp21tmp, asm: "DIVW", resultInArg0: true, clobberFlags: true}, // arg0 / arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/prove.go
if b.Func.Config.arch != "386" && b.Func.Config.arch != "amd64" { break } divr := v.Args[1] divrLim, divrLimok := ft.limits[divr.ID] divd := v.Args[0] divdLim, divdLimok := ft.limits[divd.ID] if (divrLimok && (divrLim.max < -1 || divrLim.min > -1)) || (divdLimok && divdLim.min > mostNegativeDividend[v.Op]) { // See DivisionNeedsFixUp in rewrite.go.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:30:21 UTC 2024 - 48.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Mod8 x y) => (Mod32 (SignExt8to32 x) (SignExt8to32 y)) (Mod8u x y) => (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y)) (Mod64 x y) && buildcfg.GOPPC64 >=9 => (MODSD x y) (Mod64 x y) && buildcfg.GOPPC64 <=8 => (SUB x (MULLD y (DIVD x y))) (Mod64u x y) && buildcfg.GOPPC64 >= 9 => (MODUD x y) (Mod64u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLD y (DIVDU x y))) (Mod32 x y) && buildcfg.GOPPC64 >= 9 => (MODSW x y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(Mul(32|16|8) ...) => (MULLW ...) (Mul32F ...) => (FMULS ...) (Mul64F ...) => (FMUL ...) (Mul64uhilo ...) => (MLGR ...) (Div32F ...) => (FDIVS ...) (Div64F ...) => (FDIV ...) (Div64 x y) => (DIVD x y) (Div64u ...) => (DIVDU ...) // DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor, // so a sign/zero extension of the dividend is required. (Div32 x y) => (DIVW (MOVWreg x) y) (Div32u x y) => (DIVWU (MOVWZreg x) y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0)