MSR	R29, PMEVCNTR16_EL0                // 1dea1bd5
	MSR	R11, PMEVCNTR17_EL0                // 2bea1bd5
	MSR	R16, PMEVCNTR18_EL0                // 50ea1bd5
	MSR	R2, PMEVCNTR19_EL0                 // 62ea1bd5
	MSR	R19, PMEVCNTR20_EL0                // 93ea1bd5
	MSR	R17, PMEVCNTR21_EL0                // b1ea1bd5
	MSR	R7, PMEVCNTR22_EL0                 // c7ea1bd5
	MSR	R23, PMEVCNTR23_EL0                // f7ea1bd5

	ADDQ	DX, AX
	MOVQ	AX, ret+0(FP)
	RET
fences:
	// MFENCE is instruction stream serializing and flushes the
	// store buffers on AMD. The serialization semantics of LFENCE on AMD
	// are dependent on MSR C001_1029 and CPU generation.
	// LFENCE on Intel does wait for all previous instructions to have executed.
	// Intel recommends MFENCE;LFENCE in its manuals before RDTSC to have all