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Results 1 - 7 of 7 for spre (0.17 sec)
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src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VPERMPD $216, Y7, Y7 // c4e3fd01ffd8 // Check that LEAL is permitted to use overflowing offset. LEAL 2400959708(BP)(R10*1), BP // 428dac15dcbc1b8f LEAL 3395469782(AX)(R10*1), AX // 428d8410d6c162ca // Make sure MOV CR/DR continues to work after changing its movtabs. MOVQ CR0, AX // 0f20c0 MOVQ CR0, DX // 0f20c2 MOVQ CR4, DI // 0f20e7 MOVQ AX, CR0 // 0f22c0 MOVQ DX, CR0 // 0f22c2 MOVQ DI, CR4 // 0f22e7
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 11 18:32:50 GMT 2023 - 57.6K bytes - Viewed (0) -
src/archive/zip/reader_test.go
} } func TestCVE202139293(t *testing.T) { // directory size is so large, that the check in Reader.init // overflows when subtracting from the archive size, causing // the pre-allocation check to be bypassed. data := []byte{ 0x50, 0x4b, 0x06, 0x06, 0x05, 0x06, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x4b,
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Mar 27 18:23:49 GMT 2024 - 55.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
TEXT foo(SB), DUPOK|NOSPLIT, $0 // ADD // // LTYPE1 cond imsr ',' spreg ',' reg // { // outcode($1, $2, &$3, $5, &$7); // } // Cover some operand space here too. ADD $1, R2, R3 ADD R1<<R2, R3, R4 ADD R1>>R2, R3, R4 ADD R1@>R2, R3, R4 ADD R1->R2, R3, R4 ADD R1, R2, R3 ADD R(1)<<R(2), R(3), R(4) // ADD R1<<R2, R3, R4 // LTYPE1 cond imsr ',' spreg ',' // asm doesn't support trailing comma. // {
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0) -
src/cmd/cgo/gcc.go
} else if gomips64 == "softfloat" { return []string{"-mabi=64", "-msoft-float"} } case "mips", "mipsle": if gomips == "hardfloat" { return []string{"-mabi=32", "-mfp32", "-mhard-float", "-mno-odd-spreg"} } else if gomips == "softfloat" { return []string{"-mabi=32", "-msoft-float"} } case "loong64": return []string{"-mabi=lp64d"} } return nil } func gccTmp() string {
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Thu Nov 02 16:43:23 GMT 2023 - 97K bytes - Viewed (0) -
src/bytes/bytes_test.go
func BenchmarkIndexHard2(b *testing.B) { benchmarkIndexHard(b, []byte("</pre>")) } func BenchmarkIndexHard3(b *testing.B) { benchmarkIndexHard(b, []byte("<b>hello world</b>")) } func BenchmarkIndexHard4(b *testing.B) { benchmarkIndexHard(b, []byte("<pre><b>hello</b><strong>world</strong></pre>")) } func BenchmarkLastIndexHard1(b *testing.B) { benchmarkLastIndexHard(b, []byte("<>")) }
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Jan 24 16:07:25 GMT 2024 - 56.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
VREV32 V5.B16, V5.B16 // a508206e VREV64 V2.S2, V3.S2 // 4308a00e VREV64 V2.S4, V3.S4 // 4308a04e // logical ops // // make sure constants get encoded into an instruction when it could AND R1@>33, R2 AND $(1<<63), R1 // AND $-9223372036854775808, R1 // 21004192
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 94.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
BC $16,CR0LT,0(PC) // 42000000 BCL $16,CR0LT,0(PC) // 42000001 BC $18,CR0LT,0(PC) // 42400000 MOVD SPR(3), 4(R1) // 7fe302a6fbe10004 MOVD XER, 4(R1) // 7fe102a6fbe10004 MOVD 4(R1), SPR(3) // ebe100047fe303a6 MOVD 4(R1), XER // ebe100047fe103a6 PNOP // 0700000000000000
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Apr 24 15:53:25 GMT 2024 - 49K bytes - Viewed (0)