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src/cmd/asm/internal/asm/testdata/arm.s
ADD $1, R2, R3 ADD R1<<R2, R3, R4 ADD R1>>R2, R3, R4 ADD R1@>R2, R3, R4 ADD R1->R2, R3, R4 ADD R1, R2, R3 ADD R(1)<<R(2), R(3), R(4) // ADD R1<<R2, R3, R4 // LTYPE1 cond imsr ',' spreg ',' // asm doesn't support trailing comma. // { // outcode($1, $2, &$3, $5, &nullgen); // } // LTYPE1 cond imsr ',' reg // { // outcode($1, $2, &$3, 0, &$5); // } ADD $1, R2 ADD R1<<R2, R3 ADD R1>>R2, R3
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VADDPD 8128(DX), Z28, Z29 // 62619d40586a7f VADDPD 8128(DX)(AX*2), Z0, Z29 // 6261fd48586c427f VADDPD 8128(DX)(AX*2), Z29, Z1 // 62f19540584c427f // EVEX: compressed displacement that does not fit into 8bits. VADDPD 2048(DX), X29, X0 // 62f19500588200080000 VADDPD 2048(DX), X1, X29 // 6261f50858aa00080000 VADDPD 2048(DX), X29, X28 // 6261950058a200080000
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 11 18:32:50 GMT 2023 - 57.6K bytes - Viewed (0)