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  1. src/cmd/asm/internal/asm/testdata/ppc64.s

    	// Hex constant 0x20004000000
    	MOVD $2199090364416, R5         // 60058001
    	// Hex constant 0xFFFFFE0004000000
    	MOVD $-2198956146688, R5        // 38a08001
    	// TODO: On GOPPC64={power8,power9}, this is preprocessed into MOVD $-1, R5; RLDC R5, $33, $63, R5.
    	//       This only captures the MOVD. Should the RLDC be appended to the encoding by the test?
    	// Hex constant 0xFFFFFFFE00000001
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/arm.s

    // the old assembler's (5a's) grammar and hand-writing complete
    // instructions for each rule, to guarantee we cover the same space.
    
    #include "../../../../../runtime/textflag.h"
    
    TEXT	foo(SB), DUPOK|NOSPLIT, $0
    
    // ADD
    //
    //	LTYPE1 cond imsr ',' spreg ',' reg
    //	{
    //		outcode($1, $2, &$3, $5, &$7);
    //	}
    // Cover some operand space here too.
    	ADD	$1, R2, R3
    	ADD	R1<<R2, R3, R4
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/arm64.s

    	VFMLS	V1.D2, V12.D2, V1.D2            // 81cde14e
    	VFMLS	V1.S2, V12.S2, V1.S2            // 81cda10e
    	VFMLS	V1.S4, V12.S4, V1.S4            // 81cda14e
    	VEXT	$4, V2.B8, V1.B8, V3.B8         // 2320022e
    	VEXT	$8, V2.B16, V1.B16, V3.B16      // 2340026e
    	VRBIT	V24.B16, V24.B16                // 185b606e
    	VRBIT	V24.B8, V24.B8                  // 185b602e
    	VUSHR	$56, V1.D2, V2.D2               // 2204486f
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 94.9K bytes
    - Viewed (0)
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