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tensorflow/compiler/mlir/lite/stablehlo/tests/legalize_hlo.mlir
// CHECK: return %[[VAL_4]] : tensor<?xi32> // CHECK: } func.func @relu6_unranked(%arg0: tensor<?xi32>) -> tensor<?xi32> { %0 = mhlo.constant dense<0> : tensor<i32> %1 = mhlo.constant dense<6> : tensor<i32> %2 = "chlo.broadcast_minimum"(%arg0, %1) {broadcast_dimensions = array<i64>} : (tensor<?xi32>, tensor<i32>) -> tensor<?xi32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 29 07:26:59 UTC 2024 - 340.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/fuse-tftext.mlir
%230 = "tf.Reshape"(%229, %9) {device = ""} : (tensor<i32>, tensor<0xi32>) -> tensor<i32> %231 = "tf.Pack"(%7, %230) {axis = 0 : i64, device = ""} : (tensor<i32>, tensor<i32>) -> tensor<2xi32> %232 = "tf.Mul"(%230, %8) {device = ""} : (tensor<i32>, tensor<i32>) -> tensor<i32> %233 = "tf.Pack"(%232) {axis = 0 : i64, device = ""} : (tensor<i32>) -> tensor<1xi32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 460.3K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/tables.go
VCVTR_LT_S32_F32: "VCVTR.LT.S32.F32", VCVTR_GT_S32_F32: "VCVTR.GT.S32.F32", VCVTR_LE_S32_F32: "VCVTR.LE.S32.F32", VCVTR_S32_F32: "VCVTR.S32.F32", VCVTR_ZZ_S32_F32: "VCVTR.ZZ.S32.F32", VCVTR_EQ_S32_F64: "VCVTR.EQ.S32.F64", VCVTR_NE_S32_F64: "VCVTR.NE.S32.F64", VCVTR_CS_S32_F64: "VCVTR.CS.S32.F64", VCVTR_CC_S32_F64: "VCVTR.CC.S32.F64", VCVTR_MI_S32_F64: "VCVTR.MI.S32.F64",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 16 17:57:48 UTC 2017 - 267.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/tests/legalize-tf.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon May 06 18:46:23 UTC 2024 - 335.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf.cc
// input tensor's full range. Strides for all resultant slices are all one. // // For example, the following source IR: // // %dim = "tf.Const"() {value = dense<1> : tensor<i32>} : () -> tensor<i32> // %0:3 = "tf.Split"(%dim, %input) : (tensor<i32>, tensor<4x6xf32>) -> // (tensor<4x2xf32>, tensor<4x2xf32>, tensor<4x2xf32>) // // will be converted into: // // %0 = "mhlo.slice"(%input) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 20:00:43 UTC 2024 - 291.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/optimize.mlir
// CHECK: return %0 } // CHECK-LABEL: fusedAvgPool2dRelu1 func.func @fusedAvgPool2dRelu1(%arg0: tensor<1x147x147x16xf32>) -> tensor<1x73x73x16xf32> {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 16 20:31:41 UTC 2024 - 284.1K bytes - Viewed (0)