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Results 1 - 6 of 6 for addU (0.11 sec)

  1. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

    	FSQRT:          "fsqrt",
    	FSQRTCC:        "fsqrt.",
    	ADD:            "add",
    	ADDCC:          "add.",
    	ADDO:           "addo",
    	ADDOCC:         "addo.",
    	ADDC:           "addc",
    	ADDCCC:         "addc.",
    	ADDCO:          "addco",
    	ADDCOCC:        "addco.",
    	ADDE:           "adde",
    	ADDECC:         "adde.",
    	ADDEO:          "addeo",
    	ADDEOCC:        "addeo.",
    	LI:             "li",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 334.7K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewriteS390X.go

    	v_2 := v.Args[2]
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (ADDE x y (FlagEQ))
    	// result: (ADDC x y)
    	for {
    		x := v_0
    		y := v_1
    		if v_2.Op != OpS390XFlagEQ {
    			break
    		}
    		v.reset(OpS390XADDC)
    		v.AddArg2(x, y)
    		return true
    	}
    	// match: (ADDE x y (FlagLT))
    	// result: (ADDC x y)
    	for {
    		x := v_0
    		y := v_1
    		if v_2.Op != OpS390XFlagLT {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 395.1K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/tests/optimize.mlir

    // Fusing:  %[[add1:[0-9].*]] = tfl.add %arg0, %[[add]] {fused_activation_function = "RELU"} : tensor<1xf32>
    // Fusing:  %[[relu:[0-9].*]] = "tfl.relu"(%arg0) : (tensor<1xf32>) -> tensor<1xf32>
    // Fusing:  %[[add2:[0-9].*]] = tfl.add %[[relu]], %[[add1]] {fused_activation_function = "RELU6"} : tensor<1xf32>
    // Fusing:  %[[add3:[0-9].*]] = tfl.add %[[add2]], %[[relu]] {fused_activation_function = "RELU6"} : tensor<1xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 16 20:31:41 UTC 2024
    - 284.1K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/rewritePPC64.go

    }
    func rewriteValuePPC64_OpPPC64ADDE(v *Value) bool {
    	v_2 := v.Args[2]
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	typ := &b.Func.Config.Types
    	// match: (ADDE x y (Select1 <typ.UInt64> (ADDCconst (MOVDconst [0]) [-1])))
    	// result: (ADDC x y)
    	for {
    		x := v_0
    		y := v_1
    		if v_2.Op != OpSelect1 || v_2.Type != typ.UInt64 {
    			break
    		}
    		v_2_0 := v_2.Args[0]
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 360.2K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewriteARM.go

    		break
    	}
    	// match: (ADDS x (SLL y z))
    	// result: (ADDSshiftLLreg x y z)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			x := v_0
    			if v_1.Op != OpARMSLL {
    				continue
    			}
    			z := v_1.Args[1]
    			y := v_1.Args[0]
    			v.reset(OpARMADDSshiftLLreg)
    			v.AddArg3(x, y, z)
    			return true
    		}
    		break
    	}
    	// match: (ADDS x (SRL y z))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 486.8K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tf2xla/tests/legalize-tf.mlir

        // CHECK: [[VAL5:%.+]] = mhlo.constant
        %5 = "tf.Const"()  {value = dense<1> : tensor<i32>}  : () -> tensor<i32>
        // CHECK: [[VAL6:%.+]] = mhlo.add [[ITER_ARG2]], [[VAL5]]
        %6 = mhlo.add %barg2, %5 : tensor<i32>
        // CHECK: [[VAL7:%.+]] = mhlo.add [[ITER_ARG0]], [[VAL5]]
        %7 = mhlo.add %barg0, %5 : tensor<i32>
        // CHECK: mhlo.return [[VAL7]], [[ITER_ARG1]], [[VAL6]]
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon May 06 18:46:23 UTC 2024
    - 335.5K bytes
    - Viewed (0)
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