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Results 1 - 1 of 1 for ANDshiftRLreg (0.15 sec)
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src/cmd/compile/internal/ssa/rewriteARM.go
} z := v_1.Args[1] y := v_1.Args[0] v.reset(OpARMANDshiftLLreg) v.AddArg3(x, y, z) return true } break } // match: (AND x (SRL y z)) // result: (ANDshiftRLreg x y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARMSRL { continue } z := v_1.Args[1] y := v_1.Args[0]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 486.8K bytes - Viewed (0)