Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 5 of 5 for 16xi32 (0.29 sec)

  1. tensorflow/compiler/mlir/lite/tests/optimize.mlir

      %cst_1 = arith.constant dense<[1.0e-4]> : tensor<1xf32>
      %0 = "tfl.square"(%arg0) : (tensor<2xf32>) -> tensor<2xf32>
      %1 = "tfl.sum"(%0, %cst) {keep_dims = false} : (tensor<2xf32>, tensor<1xi32>) -> tensor<f32>
      %2 = "tfl.add"(%1, %cst_1) {fused_activation_function = "NONE"} : (tensor<f32>, tensor<1xf32>) -> tensor<1xf32>
      %3 = "tfl.sqrt"(%2) : (tensor<1xf32>) -> tensor<1xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 16 20:31:41 UTC 2024
    - 284.1K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/tf2xla/tests/legalize-tf.mlir

      %0:2 = "tf.IdentityN"(%arg0, %arg1) : (tensor<1xi32>, tensor<1xf32>) -> (tensor<1xi32>, tensor<1xf32>)
      func.return %0#0, %0#1: tensor<1xi32>, tensor<1xf32>
    }
    
    // -----
    
    // CHECK-LABEL: func @stopgradient
    func.func @stopgradient(%arg0: tensor<1xi32>) -> tensor<1xi32> {
      // CHECK-NEXT:  return %arg0 : tensor<1xi32>
      %0 = "tf.StopGradient"(%arg0) : (tensor<1xi32>) -> tensor<1xi32>
      func.return %0: tensor<1xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon May 06 18:46:23 UTC 2024
    - 335.5K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/stablehlo/tests/legalize_hlo.mlir

    // CHECK:           %[[VAL_3:.*]] = "tf.LeftShift"(%[[VAL_1]], %[[VAL_0]]) : (tensor<4xi32>, tensor<1xi32>) -> tensor<4xi32>
    // CHECK:           return %[[VAL_2]], %[[VAL_3]] : tensor<4xi32>, tensor<4xi32>
    // CHECK:         }
    func.func @broadcast_shift_left(%arg0: tensor<1xi32>, %arg1: tensor<4xi32>) -> (tensor<4xi32>, tensor<4xi32>) {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed May 29 07:26:59 UTC 2024
    - 340.2K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/lite/tests/fuse-tftext.mlir

      %119 = "tf.StridedSlice"(%116, %16, %15, %16) {begin_mask = 0 : i64, device = "", ellipsis_mask = 0 : i64, end_mask = 1 : i64, new_axis_mask = 0 : i64, shrink_axis_mask = 0 : i64} : (tensor<1xi32>, tensor<1xi32>, tensor<1xi32>, tensor<1xi32>) -> tensor<0xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 460.3K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewritePPC64.go

    		if z.Op != OpPPC64MOVHZreg {
    			break
    		}
    		x := z.Args[0]
    		if !(z.Uses == 1 && c < 16) {
    			break
    		}
    		v.reset(OpPPC64CLRLSLWI)
    		v.AuxInt = int32ToAuxInt(newPPC64ShiftAuxInt(c, 16, 31, 32))
    		v.AddArg(x)
    		return true
    	}
    	// match: (SLWconst [c] z:(ANDconst [d] x))
    	// cond: z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(32-getPPC64ShiftMaskLength(d))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 360.2K bytes
    - Viewed (0)
Back to top