o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
		}

		if o.ispfx {
			if rel == nil {
				o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, v)
			} else {
				o1, o2 = pfxadd(int16(p.To.Reg), REG_R0, PFX_R_PCREL, 0)
				rel.Type = objabi.R_ADDRPOWER_PCREL34
			}
		}

	case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */

				{eventHappens: &PvcAdd},
				{podPopped: pod},
				// This gets added for the pod.
				{eventHappens: &PvAdd},
				// This doesn't get added because no plugin is interested in PvUpdate.
				{eventHappens: &PvUpdate},
			},
			wantInFlightPods:   []*v1.Pod{pod},
			wantInFlightEvents: []interface{}{pod, PvAdd},
			queueingHintMap: QueueingHintMapPerProfile{
				"": {

	// FADD <Sd>, <Sn>, <Sm>
	{0xffe0fc00, 0x1e202800, FADD, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
	// FADD <Dd>, <Dn>, <Dm>
	{0xffe0fc00, 0x1e602800, FADD, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
	// FADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>

	{AFCMOVNE, yfcmv, Px, opBytes{0xdb, 01}},
	{AFCMOVNU, yfcmv, Px, opBytes{0xdb, 03}},
	{AFCMOVU, yfcmv, Px, opBytes{0xda, 03}},
	{AFCMOVUN, yfcmv, Px, opBytes{0xda, 03}},
	{AFCOMD, yfadd, Px, opBytes{0xdc, 02, 0xd8, 02, 0xdc, 02}},  // botch
	{AFCOMDP, yfadd, Px, opBytes{0xdc, 03, 0xd8, 03, 0xdc, 03}}, // botch
	{AFCOMDPP, ycompp, Px, opBytes{0xde, 03}},
	{AFCOMF, yfmvx, Px, opBytes{0xd8, 02}},
	{AFCOMFP, yfmvx, Px, opBytes{0xd8, 03}},

	BINDERFS_SUPER_MAGIC                        = 0x6c6f6f70
	BINFMTFS_MAGIC                              = 0x42494e4d
	BPF_A                                       = 0x10
	BPF_ABS                                     = 0x20
	BPF_ADD                                     = 0x0
	BPF_ALU                                     = 0x4
	BPF_ALU64                                   = 0x7
	BPF_AND                                     = 0x50

	// compare and swap
	{i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},

	// floating point
	{i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
	{i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
	{i: 33, as: AFABS, a6: C_FREG},
	{i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
	{i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
	{i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},

{"Name":"FADD (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FADD (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FADD <Sd>, <Sn>, <Sm>","Code":"","Alias":""},

	SYS___SCALBLN_H                     = 0xADA // 2778
	SYS_SCALBLNF                        = 0xADB // 2779
	SYS___SCALBLNF_B                    = 0xADC // 2780
	SYS___SCALBLNF_H                    = 0xADD // 2781
	SYS_SCALBLNL                        = 0xADE // 2782
	SYS___SCALBLNL_B                    = 0xADF // 2783
	SYS___SCALBLNL_H                    = 0xAE0 // 2784
	SYS___SCALBN_B                      = 0xAE1 // 2785

// Copyright 2016 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

(Add(Ptr|64|32|16|8) ...) => (ADD ...)
(Add(32|64)F ...) => (FADD(S|D) ...)

(Sub(Ptr|64|32|16|8) ...) => (SUB ...)
(Sub(32|64)F ...) => (FSUB(S|D) ...)

(Mul64 ...) => (MUL ...)
(Mul(32|16|8) ...) => (MULW ...)
(Mul(32|64)F  ...) => (FMUL(S|D) ...)

(Hmul64  ...) => (MULH ...)

			rel.Off = int32(c.pc)
			rel.Siz = 4
			rel.Sym = p.To.Sym
			rel.Add = p.To.Offset
			rel.Type = objabi.R_ADDR
			o1 = 0
		}

	case 15: /* mul/mneg/umulh/umull r,[r,]r; madd/msub/fmadd/fmsub/fnmadd/fnmsub Rm,Ra,Rn,Rd */
		o1 = c.oprrr(p, p.As)

		rf := int(p.From.Reg)
		rt := int(p.To.Reg)
		var r int
		var ra int
		if p.From3Type() == obj.TYPE_REG {
			r = int(p.GetFrom3().Reg)