if isRegShiftOrExt(&p.To) {
			// extended or shifted offset register.
			c.checkShiftAmount(p, &p.To)

			o1 = c.opstrr(p, p.As, true)
			o1 |= c.encRegShiftOrExt(p, &p.To, p.To.Index) /* includes reg, op, etc */
		} else {
			// (Rn)(Rm), no extension or shift.
			o1 = c.opstrr(p, p.As, false)
			o1 |= uint32(p.To.Index&31) << 16
		}
		o1 |= uint32(p.To.Reg&31) << 5
		rf := int(p.From.Reg)

}

// Create description of operation that could not be converted.
static std::string GetOpDescriptionForDebug(Operation* inst) {
  const int kLargeElementsAttr = 16;
  std::string op_str;
  llvm::raw_string_ostream os(op_str);
  inst->getName().print(os);
  os << "(";
  if (!inst->getOperandTypes().empty()) {
    bool first = true;
    for (Type operand_type : inst->getOperandTypes()) {

	op_STPX    uint32 = 0xB211 // FORMAT_S          STORE PREFIX
	op_STRAG   uint32 = 0xE502 // FORMAT_SSE        STORE REAL ADDRESS
	op_STRL    uint32 = 0xC40F // FORMAT_RIL2       STORE RELATIVE LONG (32)
	op_STRV    uint32 = 0xE33E // FORMAT_RXY1       STORE REVERSED (32)
	op_STRVG   uint32 = 0xE32F // FORMAT_RXY1       STORE REVERSED (64)

	USHR
	USQADD
	USRA
	USUBL
	USUBL2
	USUBW
	USUBW2
	UXTB
	UXTH
	UXTL
	UXTL2
	UZP1
	UZP2
	WFE
	WFI
	XTN
	XTN2
	YIELD
	ZIP1
	ZIP2
)

var opstr = [...]string{
	ABS:       "ABS",
	ADC:       "ADC",
	ADCS:      "ADCS",
	ADD:       "ADD",
	ADDHN:     "ADDHN",
	ADDHN2:    "ADDHN2",
	ADDP:      "ADDP",
	ADDS:      "ADDS",
	ADDV:      "ADDV",