&& registerizable(b, t3)
	&& registerizable(b, t4)
	&& registerizable(b, t5)
	&& o4 == t5.Size()
	&& o3-o4 == t4.Size()
	&& o2-o3 == t3.Size()
	&& n == t2.Size() + t3.Size() + t4.Size() + t5.Size()
	=> (Store {t2} (OffPtr <tt2> [o2] dst) d1
		(Store {t3} (OffPtr <tt3> [o3] dst) d2
			(Store {t4} (OffPtr <tt4> [o4] dst) d3
				(Store {t5} (OffPtr <tt5> [0] dst) d4 mem))))

		return uint16((d >> 16) + 1)
	}
	return uint16(d >> 16)
}

func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
	o1 := uint32(0)
	o2 := uint32(0)
	o3 := uint32(0)
	o4 := uint32(0)
	o5 := uint32(0)

	//print("%v => case %d\n", p, o->type);
	switch o.type_ {
	default:
		c.ctxt.Diag("unknown type %d", o.type_)
		prasm(p)

	case 0: /* pseudo ops */
		break

		}
	default:
		panic("invalid operation")
	}
}

func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) {
	var os [5]uint32
	o1 := uint32(0)
	o2 := uint32(0)
	o3 := uint32(0)
	o4 := uint32(0)
	o5 := uint32(0)
	if false { /*debug['P']*/
		fmt.Printf("%x: %v\ttype %d\n", uint32(p.Pc), p, o.type_)
	}
	switch o.type_ {
	default:
		c.ctxt.Diag("%v: unknown asm %d", p, o.type_)