if so&0x3 != 0 {
			log.Fatalf("invalid offset for DS form load/store %v", p)
		}

	case 108: /* mov r, xoreg ==> stwx rx,ry */
		r := int(p.To.Reg)
		o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))

	case 109: /* mov xoreg, r ==> lbzx/lhzx/lwzx rx,ry, lbzx rx,ry + extsb r,r */
		r := int(p.From.Reg)

		o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))

	"⊵":                           "\u22b5",
	"▸":                           "\u25b8",
	"⧎":                        "\u29ce",
	"⥨":                         "\u2968",
	"℞":                              "\u211e",
	"ś":                          "\u015b",
	"‚":                           "\u201a",
	"≻":                              "\u227b",

		"rtrie;":                           '\U000022B5',
		"rtrif;":                           '\U000025B8',
		"rtriltri;":                        '\U000029CE',
		"ruluhar;":                         '\U00002968',
		"rx;":                              '\U0000211E',
		"sacute;":                          '\U0000015B',
		"sbquo;":                           '\U0000201A',
		"sc;":                              '\U0000227B',

		if (p.As == AFMOVD || p.As == AFMOVS) && (fc == C_REG || fc == C_ZREG || tc == C_REG || tc == C_ZREG) {
			// FMOV Rx, Fy or FMOV Fy, Rx
			o1 = FPCVTI(0, 0, 0, 0, 6)
			if p.As == AFMOVD {
				o1 |= 1<<31 | 1<<22 // 64-bit
			}
			if fc == C_REG || fc == C_ZREG {
				o1 |= 1 << 16 // FMOV Rx, Fy
			}
		} else {
			o1 = c.oprrr(p, p.As)
		}
		o1 |= uint32(p.From.Reg&31)<<5 | uint32(p.To.Reg&31)

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			zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
			if x2 != 0 {
				zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
			}
			x2 = int16(regtmp(p))
			d2 = 0
		}
		// Emits an RX instruction if an appropriate one exists and the displacement fits in 12 bits. Otherwise use an RXY instruction.
		if op, ok := c.zopstore12(p.As); ok && isU12(d2) {

	EM_MANIK         Machine = 171 /* M2000 Reconfigurable RISC Microprocessor */
	EM_CRAYNV2       Machine = 172 /* Cray Inc. NV2 vector architecture */
	EM_RX            Machine = 173 /* Renesas RX family */
	EM_METAG         Machine = 174 /* Imagination Technologies META processor architecture */
	EM_MCST_ELBRUS   Machine = 175 /* MCST Elbrus general purpose hardware architecture */

// 'go build example.com/foo/v2' writes 'foo' or 'foo.exe', not 'v2.exe'.
//
// When compiling a package from a list of .go files, the executable
// is named after the first source file.
// 'go build ed.go rx.go' writes 'ed' or 'ed.exe'.
//
// When compiling multiple packages or a single non-main package,
// build compiles the packages but discards the resulting object,
// serving only as a check that the packages can be built.
//

e-Encryption-Seal-Algorithm":"DAREv2-HMAC-SHA256","content-type":"application/octet-stream"}},{"Bucket":"buck1","Name":"go_113/src/cmd/vendor/golang.org/x/crypto/ssh/terminal/util_solaris.go","UserDef":{"X-Minio-Internal-Server-Side-Encryption-Iv":"RX+x32G/vf9P1wkReP9k3wKldAtp=","X-Minio-Internal-Server-Side-Encryption-S3-Kms-Key-Id":"my-minio-key","X-Minio-Internal-Server-Side-Encryption-S3-Kms-Sealed-Key":"IAAfAPQoCIsvhE+JXJE5cgunjyte7SWJz4L/v9ZXUiEBecn16OYtVkOi==","X-Minio-Internal-Server-Sid...