Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 10 of 15 for Alignment (0.61 sec)

  1. src/cmd/compile/internal/ssa/_gen/generic.rules

    	&& isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6)
    	&& t2.Alignment() <= t1.Alignment()
    	&& t3.Alignment() <= t1.Alignment()
    	&& t4.Alignment() <= t1.Alignment()
    	&& t5.Alignment() <= t1.Alignment()
    	&& t6.Alignment() <= t1.Alignment()
    	&& registerizable(b, t2)
    	&& registerizable(b, t3)
    	&& registerizable(b, t4)
    	&& registerizable(b, t5)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 16 22:21:05 UTC 2024
    - 135.3K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewriteLOONG64.go

    	// cond: s > 24 && logLargeCopy(v, s) || t.Alignment()%8 != 0
    	// result: (LoweredMove [t.Alignment()] dst src (ADDVconst <src.Type> src [s-moveSize(t.Alignment(), config)]) mem)
    	for {
    		s := auxIntToInt64(v.AuxInt)
    		t := auxToType(v.Aux)
    		dst := v_0
    		src := v_1
    		mem := v_2
    		if !(s > 24 && logLargeCopy(v, s) || t.Alignment()%8 != 0) {
    			break
    		}
    		v.reset(OpLOONG64LoweredMove)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 195.8K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/rewriteMIPS.go

    	// cond: (s > 16 && logLargeCopy(v, s) || t.Alignment()%4 != 0)
    	// result: (LoweredMove [int32(t.Alignment())] dst src (ADDconst <src.Type> src [int32(s-moveSize(t.Alignment(), config))]) mem)
    	for {
    		s := auxIntToInt64(v.AuxInt)
    		t := auxToType(v.Aux)
    		dst := v_0
    		src := v_1
    		mem := v_2
    		if !(s > 16 && logLargeCopy(v, s) || t.Alignment()%4 != 0) {
    			break
    		}
    		v.reset(OpMIPSLoweredMove)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 176.6K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/rewriteMIPS64.go

    	// cond: s > 24 && logLargeCopy(v, s) || t.Alignment()%8 != 0
    	// result: (LoweredMove [t.Alignment()] dst src (ADDVconst <src.Type> src [s-moveSize(t.Alignment(), config)]) mem)
    	for {
    		s := auxIntToInt64(v.AuxInt)
    		t := auxToType(v.Aux)
    		dst := v_0
    		src := v_1
    		mem := v_2
    		if !(s > 24 && logLargeCopy(v, s) || t.Alignment()%8 != 0) {
    			break
    		}
    		v.reset(OpMIPS64LoweredMove)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 211.6K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    	// result: (LoweredMove [t.Alignment()] dst src (ADDI <src.Type> [s-moveSize(t.Alignment(), config)] src) mem)
    	for {
    		s := auxIntToInt64(v.AuxInt)
    		t := auxToType(v.Aux)
    		dst := v_0
    		src := v_1
    		mem := v_2
    		if !(s <= 16 || logLargeCopy(v, s)) {
    			break
    		}
    		v.reset(OpRISCV64LoweredMove)
    		v.AuxInt = int64ToAuxInt(t.Alignment())
    		v0 := b.NewValue0(v.Pos, OpRISCV64ADDI, src.Type)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
  6. src/cmd/link/internal/ld/data.go

    	// these symbols at the beginning of their respective section if there
    	// aren't real symbols, their alignment might not match the
    	// first symbol alignment. Therefore, there are explicitly put at the
    	// beginning of their section with the same alignment.
    	if !(ctxt.DynlinkingGo() && ctxt.HeadType == objabi.Hdarwin) && !(ctxt.HeadType == objabi.Haix && ctxt.LinkMode == LinkExternal) {
    		return
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Jun 12 15:10:50 UTC 2024
    - 100.5K bytes
    - Viewed (0)
  7. src/debug/elf/elf.go

    	R_RISCV_GNU_VTINHERIT R_RISCV = 41 /* GNU C++ vtable hierarchy */
    	R_RISCV_GNU_VTENTRY   R_RISCV = 42 /* GNU C++ vtable member usage */
    	R_RISCV_ALIGN         R_RISCV = 43 /* Alignment statement */
    	R_RISCV_RVC_BRANCH    R_RISCV = 44 /* PC-relative branch offset */
    	R_RISCV_RVC_JUMP      R_RISCV = 45 /* PC-relative jump offset */
    	R_RISCV_RVC_LUI       R_RISCV = 46 /* Absolute address */
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 00:01:16 UTC 2024
    - 134.6K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/ppc64/asm9.go

    func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int {
    	switch a {
    	case 8, 16, 32, 64:
    		// By default function alignment is 16. If an alignment > 16 is
    		// requested then the function alignment must also be promoted.
    		// The function alignment is not promoted on AIX at this time.
    		// TODO: Investigate AIX function alignment.
    		if ctxt.Headtype != objabi.Haix && cursym.Func().Align < int32(a) {
    			cursym.Func().Align = int32(a)
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 13:55:28 UTC 2024
    - 156.1K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/lite/flatbuffer_export.cc

          result.Append(std::move(pad));
        }
        if (custom_option_alignment_.has_value()) {
          {
            auto alignment = custom_option_alignment_.value();
            std::string pad(alignment - result.size() % alignment, '\0');
            result.Append(std::move(pad));
          }
        }
        auto buffer = std::string(it.second.begin(), it.second.end());
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Jun 12 21:41:49 UTC 2024
    - 164.5K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/x86/asm6.go

    }
    
    // requireAlignment ensures that the function alignment is at
    // least as high as a, which should be a power of two
    // and between 8 and 2048, inclusive.
    //
    // the boolean result indicates whether the alignment meets those constraints
    func requireAlignment(a int64, ctxt *obj.Link, cursym *obj.LSym) bool {
    	if !((a&(a-1) == 0) && 8 <= a && a <= 2048) {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 146.9K bytes
    - Viewed (0)
Back to top