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Results 1 - 10 of 15 for ui64 (0.1 sec)

  1. tensorflow/compiler/mlir/lite/ir/tfl_ops.td

      let arguments = (ins
         TFL_TensorOf<[I8, I16, I32, I64, UI8, UI16, UI32, UI64, F32, F64]>:$input,
         TFL_TensorOf<[I32]>:$dilations,
         TFL_0DTensorOf<[I8, I16, I32, I64, UI8, UI16, UI32, UI64, F32, F64]>:$padding_value
      );
    
      let results = (outs TFL_TensorOf<[I8, I16, I32, I64, UI8, UI16, UI32, UI64, F32, F64]>:$output);
    }
    
    def TFL_AddOp : TFL_Op<"add", [
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jun 06 19:09:08 UTC 2024
    - 186K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/lite/stablehlo/transforms/legalize_hlo.cc

        if (!type || type.getElementType().isUnsignedInteger(64)) {
          return rewriter.notifyMatchFailure(dynamic_iota_op,
                                             "TF::RangeOp doesn't support UI64");
        }
        // Only support 1D for now.
        if (type.getRank() > 1 || dynamic_iota_op.getIotaDimension() != 0) {
          return rewriter.notifyMatchFailure(
              dynamic_iota_op, [&](::mlir::Diagnostic& diag) {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 25 16:01:03 UTC 2024
    - 154.9K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/tests/legalize-tf.mlir

      func.return %0 : tensor<1x1x5x6x7xf32>
      // CHECK-LABEL: strided_slice_big_dims
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Jun 05 01:54:33 UTC 2024
    - 153.4K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/tests/canonicalize.mlir

      %2 = "tf.Shape"(%arg0) : (tensor<?x1x2x?xf32>) -> tensor<4xi32>
      %3 = "tf.StridedSlice"(%2, %1, %0, %1) {begin_mask = 0 : i64, ellipsis_mask = 0 : i64, end_mask = 0 : i64, new_axis_mask = 0 : i64, shrink_axis_mask = 0 : i64} : (tensor<4xi32>, tensor<1xi32>, tensor<1xi32>, tensor<1xi32>) -> tensor<2xi32>
      func.return %3 : tensor<2xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 09 22:07:10 UTC 2024
    - 132.1K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tensorflow/tests/shape_inference.mlir

        %one = "tf.Const"() {value = dense<1> : tensor<4xi32>} : () -> tensor<4xi32>
        %0 = "tf.StridedSlice"(%input, %zero, %one, %one) {begin_mask = 15 : i64, device = "", ellipsis_mask = 0 : i64, end_mask = 0 : i64, new_axis_mask = 0 : i64, shrink_axis_mask = 0 : i64} : (tensor<1024x1024x1024x1024xf32>, tensor<4xi32>, tensor<4xi32>, tensor<4xi32>) -> tensor<*xf32>
    
        // CHECK: tensor<1x1x1x1xf32>
        func.return %0 : tensor<*xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jan 23 17:24:10 UTC 2024
    - 167.4K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/lite/stablehlo/tests/uniform-quantized-stablehlo-to-tfl.mlir

    func.func @dynamic_slice(
        %arg0: tensor<4x4x!quant.uniform<i8:f32, 3.000000e-01:-5>>,
        %arg1: tensor<i64>,
        %arg2: tensor<i64>
      ) -> tensor<2x1x!quant.uniform<i8:f32, 3.000000e-01:-5>> {
      %0 = "stablehlo.dynamic_slice"(%arg0, %arg1, %arg2) {
        slice_sizes = array<i64: 2, 1>
      } : (
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue May 14 17:10:32 UTC 2024
    - 106.2K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/lite/tests/prepare-composite-functions-tf.mlir

    // CHECK:           [[VAL_24:%.*]] = "tf.StridedSlice"([[VAL_20]], [[VAL_21]], [[VAL_22]], [[VAL_23]]) <{begin_mask = 6 : i64, ellipsis_mask = 0 : i64, end_mask = 6 : i64, new_axis_mask = 0 : i64, shrink_axis_mask = 1 : i64}> : (tensor<?x8x10xf32>, tensor<3xi32>, tensor<3xi32>, tensor<3xi32>) -> tensor<8x10xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 122.1K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/tensorflow/transforms/tf_passes.td

              "tf.Yield"(%6) : (tensor<i64>) -> ()
            }, {
              "tf.Yield"(%arg3) : (tensor<i64>) -> ()
            }) {_lower_using_switch_merge = true, is_stateless = false} : (tensor<i1>) -> tensor<i64>
            "tf.Yield"(%3, %4) : (tensor<i1>, tensor<i64>) -> ()
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Jun 12 21:18:05 UTC 2024
    - 99.6K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/x86/asm6.go

    	ycover[Yu8*Ymax+Yi32] = 1
    	ycover[Yi8*Ymax+Yi32] = 1
    	ycover[Ys32*Ymax+Yi32] = 1
    
    	ycover[Yi0*Ymax+Yi64] = 1
    	ycover[Yi1*Ymax+Yi64] = 1
    	ycover[Yu7*Ymax+Yi64] = 1
    	ycover[Yu2*Ymax+Yi64] = 1
    	ycover[Yu8*Ymax+Yi64] = 1
    	ycover[Yi8*Ymax+Yi64] = 1
    	ycover[Ys32*Ymax+Yi64] = 1
    	ycover[Yi32*Ymax+Yi64] = 1
    
    	ycover[Yal*Ymax+Yrb] = 1
    	ycover[Ycl*Ymax+Yrb] = 1
    	ycover[Yax*Ymax+Yrb] = 1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 146.9K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/lite/tests/ops.mlir

    }
    
    // CHECK-LABEL: testSubInt64
    func.func @testSubInt64(tensor<? x i64>, tensor<? x i64>) -> tensor<? x i64> {
    ^bb0(%arg0: tensor<? x i64>, %arg1: tensor<? x i64>):
      // CHECK: tfl.sub %arg0, %arg1 {fused_activation_function = "RELU6"}
      %0 = tfl.sub %arg0, %arg1 {fused_activation_function = "RELU6"} : tensor<? x i64>
      func.return %0#0 : tensor<? x i64>
    }
    
    // CHECK-LABEL: testMul
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jun 06 19:09:08 UTC 2024
    - 189.2K bytes
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