VPXOR      (0*32)(inp), TT0, TT0; VPXOR (1*32)(inp), TT1, TT1; VPXOR (2*32)(inp), TT2, TT2; VPXOR (3*32)(inp), TT3, TT3
	VMOVDQU    TT0, (0*32)(oup); VMOVDQU TT1, (1*32)(oup); VMOVDQU TT2, (2*32)(oup); VMOVDQU TT3, (3*32)(oup)
	VPERM2I128 $0x02, AA1, BB1, TT0; VPERM2I128 $0x02, CC1, DD1, TT1; VPERM2I128 $0x13, AA1, BB1, TT2; VPERM2I128 $0x13, CC1, DD1, TT3

(Move {t1} [n] dst p1
	mem:(Store {t2} op2:(OffPtr <tt2> [o2] p2) d1
		(Store {t3} op3:(OffPtr <tt3> [0] p3) d2 _)))
	&& isSamePtr(p1, p2) && isSamePtr(p2, p3)
	&& t2.Alignment() <= t1.Alignment()
	&& t3.Alignment() <= t1.Alignment()
	&& registerizable(b, t2)
	&& registerizable(b, t3)
	&& o2 == t3.Size()
	&& n == t2.Size() + t3.Size()
	=> (Store {t2} (OffPtr <tt2> [o2] dst) d1
		(Store {t3} (OffPtr <tt3> [0] dst) d2 mem))