REG_CR4EQ
	REG_CR4SO
	REG_CR5LT
	REG_CR5GT
	REG_CR5EQ
	REG_CR5SO
	REG_CR6LT
	REG_CR6GT
	REG_CR6EQ
	REG_CR6SO
	REG_CR7LT
	REG_CR7GT
	REG_CR7EQ
	REG_CR7SO

	/* Align FPR and VSR vectors such that when masked with 0x3F they produce
	   an equivalent VSX register. */
	/* F0=4160 ... F31=4191 */
	REG_F0
	REG_F1
	REG_F2
	REG_F3
	REG_F4
	REG_F5
	REG_F6
	REG_F7
	REG_F8

// REG_Rx & 31 == x
// REG_Fx & 31 == x
// REG_Vx & 31 == x
// REG_VSx & 63 == x
// REG_SPRx & 1023 == x
// REG_CRx & 7 == x
//
// VR and FPR disjointly overlap VSR, interpreting as VSR registers should produce the correctly overlapped VSR.
// REG_FPx & 63 == x
// REG_Vx & 63 == x + 32
func TestRegValueAlignment(t *testing.T) {
	tstFunc := func(rstart, rend, msk, rout int) {
		for i := rstart; i <= rend; i++ {

	VXOR	IN0, KEY, IN0                    // vxor 1,1,3
	STXVD2X	IN0, (R0+OUTENC)
	STXVD2X	IN0, (R0+OUTDEC)

	RET

l192:
	LXSDX	(INP+R0), IN1                    // Load next 8 bytes into upper half of VSR.
	XXBRD_ON_LE(IN1, IN1)                    // and convert to BE ordering on LE hosts.
	MOVD	$4, CNT                          // li 7,4
	STXVD2X	IN0, (R0+OUTENC)
	STXVD2X	IN0, (R0+OUTDEC)
	ADD	$16, OUTENC, OUTENC