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Results 1 - 10 of 30 for r2r1 (0.1 sec)
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src/runtime/duff_loong64.s
ADDV $8, R21 MOVV (R20), R30 ADDV $8, R20 MOVV R30, (R21) ADDV $8, R21 MOVV (R20), R30 ADDV $8, R20 MOVV R30, (R21) ADDV $8, R21 MOVV (R20), R30 ADDV $8, R20 MOVV R30, (R21) ADDV $8, R21 MOVV (R20), R30 ADDV $8, R20 MOVV R30, (R21) ADDV $8, R21 MOVV (R20), R30 ADDV $8, R20 MOVV R30, (R21) ADDV $8, R21 MOVV (R20), R30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:21 UTC 2023 - 11.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
ORRW $16252928, ZR, R21 // f5130d32 MOVD $-4260607558625, R11 // eb6b16b2 MOVD R30, R7 // e7031eaa MOVKW $(3905<<0), R21 // MOVKW $3905, R21 // 35e88172 MOVKW $(3905<<16), R21 // MOVKW $255918080, R21 // 35e8a172
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/runtime/sys_linux_ppc64x.s
MOVD g_m(g), R21 // R21 = m MOVD $0, R3 // CLOCK_REALTIME MOVD runtime·vdsoClockgettimeSym(SB), R12 // Check for VDSO availability CMP R12, $0 BEQ fallback // Set vdsoPC and vdsoSP for SIGPROF traceback. // Save the old values on stack and restore them on exit, // so this function is reentrant. MOVD m_vdsoPC(R21), R4 MOVD m_vdsoSP(R21), R5 MOVD R4, 32(R1) MOVD R5, 40(R1)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 18.1K bytes - Viewed (0) -
src/runtime/sys_linux_arm64.s
MOVD RSP, R1 MOVD g_m(g), R21 // R21 = m // Set vdsoPC and vdsoSP for SIGPROF traceback. // Save the old values on stack and restore them on exit, // so this function is reentrant. MOVD m_vdsoPC(R21), R2 MOVD m_vdsoSP(R21), R3 MOVD R2, 8(RSP) MOVD R3, 16(RSP) MOVD $ret-8(FP), R2 // caller's SP MOVD LR, m_vdsoPC(R21) MOVD R2, m_vdsoSP(R21) MOVD m_curg(R21), R0 CMP g, R0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 24 18:53:44 UTC 2023 - 16.7K bytes - Viewed (0) -
src/hash/crc32/crc32_ppc64le.s
XOR R21,R24,R21 // xor done R24 MOVWZ (R10)(R8),R25 // tab[4][crc>>24] RLDICL $48,R7,$56,R24 // crc>>16&0xFF XOR R21,R25,R21 // xor done R25 ADD $1024,R10,R10 // &tab[5] SLD $2,R24,R24 // crc>>16&0xFF*4 MOVWZ (R10)(R24),R26 // tab[5][crc>>16&0xFF] XOR R21,R26,R21 // xor done R26 RLDICL $56,R7,$56,R25 // crc>>8 ADD $1024,R10,R10 // &tab[6] SLD $2,R25,R25 // crc>>8&FF*2 MOVBZ R7,R26 // crc&0xFF
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 12:09:50 UTC 2024 - 13.1K bytes - Viewed (0) -
src/math/big/arith_ppc64x.s
loop: MOVD 8(R8), R20 // R20 = x[i] MOVD 16(R8), R21 // R21 = x[i+1] MOVD 24(R8), R22 // R22 = x[i+2] MOVDU 32(R8), R23 // R23 = x[i+3] MULLD R9, R20, R24 // R24 = z0[i] MULHDU R9, R20, R20 // R20 = z1[i] ADDC R4, R24 // R24 = z0[i] + c MULLD R9, R21, R25 MULHDU R9, R21, R21 ADDE R20, R25 MULLD R9, R22, R26 MULHDU R9, R22, R22
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 16.8K bytes - Viewed (0) -
src/internal/bytealg/index_ppc64x.s
MOVD $2, R15 // Set up index // Set up masks for use with VSEL MOVD $0xff, R21 // Set up mask 0xff000000ff000000... SLD $24, R21 MTVSRD R21, V10 VSPLTW $1, V10, V29 VSLDOI $2, V29, V29, V30 // Mask 0x0000ff000000ff00... MOVD $0xffff, R21 SLD $16, R21 MTVSRD R21, V10 VSPLTW $1, V10, V31 // Mask 0xffff0000ffff0000... VSPLTW $0, V0, V1 // Splat 1st word of separator
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 31.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// } SLL $19, R22, R21 // 0016acc0 SLLV $19, R22, R21 // 0016acf8 SRL $31, R6, R17 // 00068fc2 SRLV $31, R6, R17 // 00068ffa SRA $8, R8, R19 // 00089a03 SRAV $19, R8, R7 // 00083cfb ROTR $12, R8, R3 // 00281b02 ROTRV $8, R22, R22 // 0036b23a // LSHW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL $19, R21 // 0015acc0 SLLV $19, R21 // 0015acf8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/math/big/arith_arm64.s
LSL R4, R6, R20 LSR R3, R6 ORR R8, R20 LSL R4, R7, R21 LSR R3, R7, R8 ORR R6, R21 STP.P (R20, R21), 16(R0) SUB $2, R1 loop: CBZ R1, done LDP.P 32(R2), (R10, R11) LDP -16(R2), (R12, R13) LSL R4, R10, R20 LSR R3, R10 ORR R8, R20 // z[i] = (x[i] >> s) | (x[i+1] << (64 - s)) LSL R4, R11, R21 LSR R3, R11 ORR R10, R21 LSL R4, R12, R22 LSR R3, R12 ORR R11, R22
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 11.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
// large or unaligned move // arg0 = address of dst memory (in R21, changed as side effect) // arg1 = address of src memory (in R20, changed as side effect) // arg2 = address of the last element of src // arg3 = mem // auxint = alignment // returns mem // MOVx (R20), Rtmp // MOVx Rtmp, (R21) // ADDV $sz, R20 // ADDV $sz, R21 // BGEU Rarg2, R20, -4(PC) { name: "LoweredMove",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0)