FMULAD	F0, F1             // ERROR "illegal combination"
	FMULAF	F0, F1             // ERROR "illegal combination"
	FMULSD	F0, F1             // ERROR "illegal combination"
	FMULSF	F0, F1             // ERROR "illegal combination"
	FNMULAD	F0, F1             // ERROR "illegal combination"
	FNMULAF	F0, F1             // ERROR "illegal combination"
	FNMULSD	F0, F1             // ERROR "illegal combination"

        }
        if (f1.isDirectory()) {
            return f1name.compareToIgnoreCase(f2.getName());
        }
        diff = f1.length() - f2.length();
        if (diff == 0) {
            return f1name.compareToIgnoreCase(f2.getName());
        }
        return diff > 0 ? -1 : 1;
    }

    /**
     * Compares two SMB files by file type/extension.
     * @param f1 first file to compare

        }
        if (f1.isDirectory()) {
            return f1name.compareToIgnoreCase(f2.getName());
        }
        diff = f1.length() - f2.length();
        if (diff == 0) {
            return f1name.compareToIgnoreCase(f2.getName());
        }
        return diff > 0 ? -1 : 1;
    }

    /**
     * Compares two SMB files by file type/extension.
     * @param f1 first file to compare

//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	ABSD	F1, F2

//	LFADD freg ',' freg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	ADDD	F1, F2

//	LFADD freg ',' freg ',' freg
//	{
//		outcode(int($1), &$2, int($4.Reg), &$6);
//	}
	ADDD	F1, F2, F3

//	LFCMP freg ',' freg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	CMPEQD	F1, F2


//
// WORD
//

	FIEBR	$0, F0, F1             // b3570010
	FIDBR	$7, F2, F3             // b35f7032
	FMADD	F1, F1, F1             // b31e1011
	FMADDS	F1, F2, F3             // b30e3012
	FMSUB	F4, F5, F5             // b31f5045
	FMSUBS	F6, F6, F7             // b30f7066
	LCDBR	F0, F2                 // b3130020
	LPDFR	F1, F2                 // b3700021
	LNDFR	F3, F4                 // b3710043

        assertTrue(crawlingConfigHelper.getPipeline("XXX").isEmpty());
        assertTrue(crawlingConfigHelper.getPipeline("W1").isEmpty());
        assertTrue(crawlingConfigHelper.getPipeline("F1").isEmpty());
        assertTrue(crawlingConfigHelper.getPipeline("D1").isEmpty());
        assertEquals("wp", crawlingConfigHelper.getPipeline("W1P").get());

	FCLASSF		F4, F5		// 85341401
	FCLASSD		F4, F5		// 85381401

	FFINTFW		F0, F1		// 01101d01
	FFINTFV		F0, F1		// 01181d01
	FFINTDW		F0, F1		// 01201d01
	FFINTDV		F0, F1		// 01281d01
	FTINTWF		F0, F1		// 01041b01
	FTINTWD		F0, F1		// 01081b01
	FTINTVF		F0, F1		// 01241b01
	FTINTVD		F0, F1		// 01281b01

	FMAXAF		F4, F5, F6	// a6900c01
	FMAXAF		F4, F5		// a5900c01

	PNOP                                    // 0700000000000000
	PSTB R1, $1, 12345678(R2)               // 061000bc9822614e
	PSTD R1, $1, 12345678(R2)               // 041000bcf422614e
	PSTFD F1, $1, 12345678(R2)              // 061000bcd822614e
	PSTFS F1, $1, 123456789(R7)             // 0610075bd027cd15
	PSTH R1, $1, 12345678(R2)               // 061000bcb022614e
	PSTQ R2, $1, 12345678(R2)               // 041000bcf042614e

// the validate function from being run and TestRISCVValidation will report missing
// errors.

TEXT validation(SB),$0
	SRLI	$1, X5, F1			// ERROR "expected integer register in rd position but got non-integer register F1"
	SRLI	$1, F1, X5			// ERROR "expected integer register in rs1 position but got non-integer register F1"

	//
	// "V" Standard Extension for Vector Operations, Version 1.0
	//

	MOVBU	X5, (X6)			// ERROR "unsupported unsigned store"
	MOVHU	X5, (X6)			// ERROR "unsupported unsigned store"
	MOVWU	X5, (X6)			// ERROR "unsupported unsigned store"
	MOVF	F0, F1, F2			// ERROR "illegal MOV instruction"
	MOVD	F0, F1, F2			// ERROR "illegal MOV instruction"
	MOV	X10, X11, X12			// ERROR "illegal MOV instruction"
	MOVW	X10, X11, X12			// ERROR "illegal MOV instruction"