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Results 1 - 5 of 5 for cvt4 (0.04 sec)

  1. src/cmd/compile/internal/test/float_test.go

    func TestFloatConvert(t *testing.T) {
    	if got := cvt1(3.5); got != 3 {
    		t.Errorf("cvt1 got %d, wanted 3", got)
    	}
    	if got := cvt2(3.5); got != 3 {
    		t.Errorf("cvt2 got %d, wanted 3", got)
    	}
    	if got := cvt3(3.5); got != 3 {
    		t.Errorf("cvt3 got %d, wanted 3", got)
    	}
    	if got := cvt4(3.5); got != 3 {
    		t.Errorf("cvt4 got %d, wanted 3", got)
    	}
    	if got := cvt5(3.5); got != 3 {
    		t.Errorf("cvt5 got %d, wanted 3", got)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 05 17:54:15 UTC 2022
    - 12.5K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/lite/tests/const-fold.mlir

      // CHECK-DAG: [[cst4:%.*]] = arith.constant dense<2.000000e+00> : tensor<f32>
      // CHECK-DAG: [[cst5:%.*]] = arith.constant dense<5.000000e-01> : tensor<f32>
      // CHECK-DAG: [[cst6:%.*]] = arith.constant dense<4.000000e+00> : tensor<f32>
      // CHECK: return [[cst0]], [[cst1]], [[cst2]], [[cst3]], [[cst4]], [[cst5]], [[cst6]]
    
      %7 = "tfl.abs"(%0) : (tensor<f32>) -> tensor<f32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 45.8K bytes
    - Viewed (0)
  3. src/crypto/tls/testdata/Client-TLSv13-ClientCert-RSA-RSAPSS

    000000c0  c1 8a a9 51 24 20 86 dc  99 ac d2 28 af 7b 2d 6e  |...Q$ .....(.{-n|
    000000d0  16 9b 71 71 82 00 94 51  a4 4f 22 c1 26 a2 6f 67  |..qq...Q.O".&.og|
    000000e0  d9 45 ff 80 13 39 16 0f  9c 43 76 54 e5 12 0f 89  |.E...9...CvT....|
    000000f0  95 ed 75 df eb cb 6b d2  77 fd fa 37 d7 a3 31 b5  |..u...k.w..7..1.|
    00000100  61 47 69 8f 99 55 70 d0  96 b0 f7 a9 1b 53 69 a3  |aGi..Up......Si.|
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 22:33:38 UTC 2024
    - 10.9K bytes
    - Viewed (0)
  4. src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go

    	case Reg:
    		regenum := uint16(a)
    		regno := uint16(a) & 31
    
    		if regenum >= uint16(B0) && regenum <= uint16(Q31) {
    			if strings.HasPrefix(inst.Op.String(), "F") || strings.HasSuffix(inst.Op.String(), "CVTF") || fOpsWithoutFPrefix[inst.Op] {
    				// FP registers are the same ones as SIMD registers
    				// Print Fn for scalar variant to align with assembler (e.g., FCVT, SCVTF, UCVTF, etc.)
    				return fmt.Sprintf("F%d", regno)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 16 22:24:28 UTC 2022
    - 17K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/MIPS.rules

    (Signmask x) => (SRAconst x [31])
    (Zeromask x) => (NEG (SGTU x (MOVWconst [0])))
    (Slicemask <t> x) => (SRAconst (NEG <t> x) [31])
    
    // float-int conversion
    (Cvt32to(32|64)F ...) => (MOVW(F|D) ...)
    (Cvt(32|64)Fto32 ...) => (TRUNC(F|D)W ...)
    (Cvt32Fto64F ...) => (MOVFD ...)
    (Cvt64Fto32F ...) => (MOVDF ...)
    
    (CvtBoolToUint8 ...) => (Copy ...)
    
    (Round(32|64)F ...) => (Copy ...)
    
    // comparisons
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 35.3K bytes
    - Viewed (0)
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