if s.ch != '+' {
			goto assignop
		}
		s.nextch()
		s.nlsemi = true
		s.tok = _IncOp

	case '-':
		s.nextch()
		s.op, s.prec = Sub, precAdd
		if s.ch != '-' {
			goto assignop
		}
		s.nextch()
		s.nlsemi = true
		s.tok = _IncOp

	case '*':
		s.nextch()
		s.op, s.prec = Mul, precMul
		// don't goto assignop - want _Star token
		if s.ch == '=' {

		}

		// initialize with attrs, conds
		if len(db.Statement.assigns) > 0 {
			result.assignInterfacesToValue(db.Statement.assigns...)
		}

		return tx.Create(dest)
	} else if len(db.Statement.assigns) > 0 {
		exprs := tx.Statement.BuildCondition(db.Statement.assigns[0], db.Statement.assigns[1:]...)
		assigns := map[string]interface{}{}
		for i := 0; i < len(exprs); i++ {
			expr := exprs[i]

//  variables to match the TPUExecute op. This is optional in some context,
//  e.g., guaranteed by replication.
//  - `check_same_region` specifies whether the reads/assigns need to be in the
//  same region as `execute`. This is needed if `execute` is inside ReplicateOp.
VariableAccessesForTPUExecute BuildVariableAccessInfo(
    tf_device::LaunchOp execute_launch,

        expect:
        bean.name == "<display name>"

        beanWithNoName.name.startsWith("${UsesToStringInConstructor.name}_Decorated@")
    }

    def "assigns display name to read only property of type Property<T>"() {
        given:
        def finalReadOnlyBean = create(HasReadOnlyFinalProperty, Describables.of("<display name>"))

        expect:
        bean.bean.name == "property 'bean'"
        beanWithDisplayName.bean.name == "<display-name> property 'bean'"
    }

    def "assigns display name to nested object when owner has toString() implementation"() {
        def bean = create(NestedBeanClassWithToString)
        def beanWithDisplayName = create(NestedBeanClassWithToString, Describables.of("<display-name>"))

			panic("unreachable")
		}
	}

	switch ffd.fd.net {
	case "tcp", "tcp4", "tcp6":
		if addr == nil {
			return assignIP(new(TCPAddr))
		}
		return assignIP(addr)

	case "udp", "udp4", "udp6":
		if addr == nil {
			return assignIP(new(UDPAddr))
		}
		return assignIP(addr)

	case "unix", "unixgram", "unixpacket":
		uaddr, ok := addr.(*UnixAddr)
		if !ok && addr != nil {
			return &AddrError{

		return ir.OXXX, why
	}

	// 1. src can be assigned to dst.
	op, why := assignOp(src, dst)
	if op != ir.OXXX {
		return op, why
	}

	// The rules for interfaces are no different in conversions
	// than assignments. If interfaces are involved, stop now
	// with the good message from assignop.
	// Otherwise clear the error.
	if src.IsInterface() || dst.IsInterface() {
		return ir.OXXX, why
	}

  // CHECK-NEXT: return %[[READ_3]]
  func.return %read3 : tensor<8xf32>
}

// -----

// Tests that the pass does merge reads/assigns if there are resource accesses
// in between which are not interfering.
// For %arg0 and %arg1 both reads and assigns are merged, for %arg3 and %arg4
// only reads are merged.

// CHECK-LABEL: func @non_interfering_accesses

		x.limbs = make([]uint, n)
		return x
	}
	clear(x.limbs)
	x.limbs = x.limbs[:n]
	return x
}

// set assigns x = y, optionally resizing x to the appropriate size.
func (x *Nat) set(y *Nat) *Nat {
	x.reset(len(y.limbs))
	copy(x.limbs, y.limbs)
	return x
}

// setBig assigns x = n, optionally resizing n to the appropriate size.
//
// The announced length of x is set based on the actual bit size of the input,

        return transpose;
      }
    }
  }
  return nullptr;
}

#define GEN_PASS_DEF_LAYOUTASSIGNMENTPASS
#include "tensorflow/compiler/mlir/tensorflow/transforms/tf_passes.h.inc"

// LayoutAssignmentPass assigns optimal data layout (data format) for all
// layout sensitive operations.
class LayoutAssignmentPass
    : public impl::LayoutAssignmentPassBase<LayoutAssignmentPass> {
 public:
  LayoutAssignmentPass() = default;