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src/cmd/asm/internal/asm/testdata/riscv64.s
// 2.4: Integer Computational Instructions ADDI $2047, X5 // 9382f27f ADDI $-2048, X5 // 93820280 ADDI $2048, X5 // 9382024093820240 ADDI $-2049, X5 // 938202c09382f2bf ADDI $4094, X5 // 9382f27f9382f27f ADDI $-4096, X5 // 9382028093820280 ADDI $4095, X5 // b71f00009b8fffffb382f201 ADDI $-4097, X5 // b7ffffff9b8fffffb382f201 ADDI $2047, X5, X6 // 1383f27f ADDI $-2048, X5, X6 // 13830280
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Fri Oct 25 12:05:29 UTC 2024 - 16.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// LAND/LXOR/LOR imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } AND $11, R17, R7 // 3227000b XOR $341, R1, R23 // 38370155 OR $254, R25, R13 // 372d00fe // // move immediate: macro for lui+or, addi, addis, and other combinations // // LMOVW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW $1, R1 MOVV $1, R1 // LMOVW ximm ',' rreg // { // outcode(int($1), &$2, 0, &$4);
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0)