VLSE8V		(X10), X10, X11			// ERROR "expected vector register in vd position"
	VLSE8V		(V1), X10, V3			// ERROR "expected integer register in rs1 position"
	VLSE8V		(X10), V1, V0, V3		// ERROR "expected integer register in rs2 position"
	VSSE8V		V3, (X10)			// ERROR "expected integer register in rs2 position"
	VSSE8V		X10, X11, (X10)			// ERROR "expected vector register in vd position"
	VSSE8V		V3, X11, (V1)			// ERROR "expected integer register in rs1 position"

	//
	VSETIVLI	X10, E32, M2, TA, MA, X12	// ERROR "expected immediate value"
	VLE8V		(X10), V1, V3			// ERROR "invalid vector mask register"
	VSE8V		V3, V1, (X10)			// ERROR "invalid vector mask register"
	VLSE8V		(X10), X10, V1, V3		// ERROR "invalid vector mask register"
	VSSE8V		V3, X11, V1, (X10)		// ERROR "invalid vector mask register"
	VLUXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"

	{"R12", "R12"},
	{"R13", "R13"},
	{"R14", "R14"},
	{"R15", "R15"},
	{"R8", "R8"},
	{"R9", "R9"},
	{"g", "R14"},
	{"SI", "SI"},
	{"SP", "SP"},
	{"X0", "X0"},
	{"X1", "X1"},
	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},
	{"X15", "X15"},
	{"X2", "X2"},
	{"X3", "X3"},
	{"X4", "X4"},
	{"X5", "X5"},
	{"X6", "X6"},
	{"X7", "X7"},

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,
    X22,
    X23,
    X24,
    X25,
    X26,
    X27,

	XVMOVQ		R7, X9.W[2]     // e9c8eb76
	XVMOVQ		R8, X10.V[2]    // 0ae9eb76

	// Duplicate general-purpose register to vector
	VMOVQ		R4, V2.B16      // 82009f72
	VMOVQ		R5, V3.H8       // a3049f72
	VMOVQ		R6, V4.W4       // c4089f72
	VMOVQ		R7, V5.V2       // e50c9f72
	XVMOVQ		R16, X31.B32    // 1f029f76
	XVMOVQ		R17, X28.H16    // 3c069f76
	XVMOVQ		R18, X10.W8     // 4a0a9f76
	XVMOVQ		R19, X9.V4      // 690e9f76