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src/cmd/asm/internal/asm/operand_test.go
{"[k3-k6]", "register list: bad low register in `[k3`"}, {"[X0]", "register list: expected '-' after `[X0`, found ']'"}, {"[X0-]", "register list: bad high register in `[X0-]`"}, {"[X0-x]", "register list: bad high register in `[X0-x`"}, {"[X0-X1-X2]", "register list: expected ']' after `[X0-X1`, found '-'"}, {"[X0,X3]", "register list: expected '-' after `[X0`, found ','"}, {"[X0,X1,X2,X3]", "register list: expected '-' after `[X0`, found ','"},Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue Aug 29 18:31:05 GMT 2023 - 23.9K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/riscv64validation.s
CJR X0 // ERROR "cannot use register X0 in rs1" CJR X10, X11 // ERROR "expected no register in rs2" CJALR X0 // ERROR "cannot use register X0 in rs1" CJALR X10, X11 // ERROR "expected no register in rd" CBEQZ X5, 1(PC) // ERROR "expected integer prime register in rs1" CBNEZ X5, 1(PC) // ERROR "expected integer prime register in rs1" CLI $3, X0 // ERROR "cannot use register X0 in rd"
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Nov 13 12:17:37 GMT 2025 - 42.1K bytes - Click Count (0) -
cmd/erasure-decode_test.go
const size = 12 * 1024 * 1024 b.Run(" 00|00 ", func(b *testing.B) { benchmarkErasureDecode(2, 2, 0, 0, size, b) }) b.Run(" 00|X0 ", func(b *testing.B) { benchmarkErasureDecode(2, 2, 0, 1, size, b) }) b.Run(" X0|00 ", func(b *testing.B) { benchmarkErasureDecode(2, 2, 1, 0, size, b) }) b.Run(" X0|X0 ", func(b *testing.B) { benchmarkErasureDecode(2, 2, 1, 1, size, b) }) } func BenchmarkErasureDecode_4_64KB(b *testing.B) {
Created: Sun Apr 05 19:28:12 GMT 2026 - Last Modified: Fri Aug 29 02:39:48 GMT 2025 - 21K bytes - Click Count (0) -
cmd/erasure-encode_test.go
b.Run(" 00|X0 ", func(b *testing.B) { benchmarkErasureEncode(2, 2, 0, 1, size, b) }) b.Run(" X0|00 ", func(b *testing.B) { benchmarkErasureEncode(2, 2, 1, 0, size, b) }) } func BenchmarkErasureEncode_4_64KB(b *testing.B) { const size = 64 * 1024 b.Run(" 00|00 ", func(b *testing.B) { benchmarkErasureEncode(2, 2, 0, 0, size, b) })
Created: Sun Apr 05 19:28:12 GMT 2026 - Last Modified: Fri Aug 29 02:39:48 GMT 2025 - 11.8K bytes - Click Count (0) -
guava-tests/benchmark/com/google/common/base/EnumsBenchmark.java
retVal &= Enums.getIfPresent(enumType, sampleData[i & 255]).isPresent(); } return retVal; } private enum SmallEnum { X0, X1, X2 } private enum MediumEnum { X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16,
Created: Fri Apr 03 12:43:13 GMT 2026 - Last Modified: Thu Dec 19 18:03:30 GMT 2024 - 29.4K bytes - Click Count (0) -
src/test/java/org/codelibs/fess/ds/callback/FileListIndexUpdateCallbackImplTest.java
@Test public void test_mergeResponseData_keyConflict() { Map<String, Object> dataMap = new HashMap<>(); dataMap.put("x", "X0"); Map<String, Object> responseDataMap = new HashMap<>(); responseDataMap.put("x", "X1"); indexUpdateCallback.mergeResponseData(dataMap, responseDataMap); assertEquals(1, dataMap.size());Created: Tue Mar 31 13:07:34 GMT 2026 - Last Modified: Wed Jan 14 14:29:07 GMT 2026 - 19.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/asm.go
prog.To.Type = obj.TYPE_CONST x0 := p.getConstant(prog, op, &a[0]) x1 := p.getConstant(prog, op, &a[1]) x2 := int64(p.getRegister(prog, op, &a[2])) x3 := int64(p.getRegister(prog, op, &a[3])) x4 := int64(p.getRegister(prog, op, &a[4])) x5 := p.getConstant(prog, op, &a[5]) // Cond is handled specially for this instruction. offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5) if !ok {
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Fri Mar 20 17:02:17 GMT 2026 - 27.5K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512_ifma.s
VPMADD52HUQ X7, X11, K1, X18 // 62e2a509b5d7 VPMADD52HUQ X0, X11, K1, X18 // 62e2a509b5d0 VPMADD52HUQ 17(SP)(BP*2), X11, K1, X18 // 62e2a509b5946c11000000 VPMADD52HUQ -7(DI)(R8*4), X11, K1, X18 // 62a2a509b59487f9ffffff VPMADD52HUQ X7, X31, K1, X18 // 62e28501b5d7 VPMADD52HUQ X0, X31, K1, X18 // 62e28501b5d0
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue May 22 14:57:15 GMT 2018 - 13.2K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512_vbmi.s
VPMULTISHIFTQB X14, X20, K5, X0 // 62d2dd0583c6 VPMULTISHIFTQB 17(SP)(BP*1), X20, K5, X0 // 62f2dd0583842c11000000 VPMULTISHIFTQB -7(CX)(DX*8), X20, K5, X0 // 62f2dd058384d1f9ffffff VPMULTISHIFTQB X9, X7, K5, X0 // 62d2c50d83c1 VPMULTISHIFTQB X7, X7, K5, X0 // 62f2c50d83c7
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue May 22 14:57:15 GMT 2018 - 28.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/aes_avx512f.s
VAESDEC X24, X0, X31 // 62027d08def8 or 6202fd08def8 VAESDEC X20, X0, X31 // 62227d08defc or 6222fd08defc VAESDEC X7, X0, X31 // 62627d08deff or 6262fd08deff VAESDEC -7(DI)(R8*1), X0, X31 // 62227d08debc07f9ffffff or 6222fd08debc07f9ffffff
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue May 22 14:57:15 GMT 2018 - 29K bytes - Click Count (0)