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src/cmd/asm/internal/asm/testdata/riscv64validation.s
VLUXEI8V (X10), V2, X11 // ERROR "expected vector register in vd position" VLUXEI8V (X10), V2, X11 // ERROR "expected vector register in vd position" VLUXEI8V (V1), V2, V3 // ERROR "expected integer register in rs1 position" VLUXEI8V (X10), X11, V0, V3 // ERROR "expected vector register in vs2 position" VSUXEI8V X10, V2, (X10) // ERROR "expected vector register in vd position"
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Nov 13 12:17:37 GMT 2025 - 42.1K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
XVMOVQ X1.W[2], R7 // 27c8ef76 XVMOVQ X6.V[2], R8 // c8e8ef76 XVMOVQ X8.WU[2], R7 // 07c9f376 XVMOVQ X31.VU[2], R8 // e8ebf376 // Move general-purpose register to a vector element: VMOVQ Rn, <Vd>.<T>[index] VMOVQ R4, V2.B[0] // 8280eb72 VMOVQ R4, V3.B[1] // 8384eb72 VMOVQ R5, V4.B[3] // a48ceb72 VMOVQ R6, V5.H[2] // c5c8eb72 VMOVQ R7, V6.W[2] // e6e8eb72
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Nov 27 00:46:52 GMT 2025 - 44.5K bytes - Click Count (0) -
cmd/testdata/xl-meta-merge.zip
w’‹¯¦§‘ü[ 8áñ.}¨ò=ò„Ek@ïjrsJ¾Aeæ©zãqmp¨o|þO{xˆæRCÙ]eZ¢LGSìܲwònoŠ—U`= qÖ\ H¬†:ñyòz€i¦Kct¦ævo}}ï|†\ßrèátw¼Wl¸Vâm¨pU_z†wãMfûR}¦Jñ¢ ^|VVœ½£• ‹®¸¸´¾‘ˆ ’ŒŠ ClHˆè¥½&ýô 1kNd®zøG¾Öwo@†w^eH»¦ i & 2„!yM„oeZ†ßQK¾r^e„†Tw__Ip x{‚O\IKzïˆxßMmeÜSª¼SBz[Gf¨ñ@tKIVq4€}VD öDíSÉï þÜÁ<ÅíÒÀÍÆîõ Ñj2ÜPq ?kx› ¾IcDTEr¸Ö^moC†{{x CjqY<å+`n=;ÜŠy_]òA°iò[¾ ½«gk}Ð}xû4 ï¢TyU~’†ÕyEr¦qY²Vpï² ûZ !~YExzˆàYuj¼åu]e{z~huòG°VñU~º² eiˆV À 7Eqò ÄOûp %j_GòȺJQMô§¼¯ÜmSZ½ysivq½÷ @ûY§oô}w`V«_å·¾Nñ~°}ñre¨iV`w~e}@ûYl _l„Iɯ¦%¾xøgª@o{Rºom_Qãvfding...Created: Sun Apr 05 19:28:12 GMT 2026 - Last Modified: Fri Mar 08 17:50:48 GMT 2024 - 30.2K bytes - Click Count (0)