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Results 1 - 10 of 10 for SIMD (0.08 sec)
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src/vendor/golang.org/x/sys/cpu/cpu.go
HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64) HasSSE3 bool // Streaming SIMD extension 3 HasSSSE3 bool // Supplemental streaming SIMD extension 3 HasSSE41 bool // Streaming SIMD extension 4 and 4.1 HasSSE42 bool // Streaming SIMD extension 4 and 4.2 _ CacheLinePad }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 08 16:12:58 UTC 2024 - 12.1K bytes - Viewed (0) -
src/cmd/go/internal/work/security.go
re(`-fmessage-length=(.+)`), re(`-f(no-)?modules`), re(`-f(no-)?objc-arc`), re(`-f(no-)?objc-nonfragile-abi`), re(`-f(no-)?objc-legacy-dispatch`), re(`-f(no-)?omit-frame-pointer`), re(`-f(no-)?openmp(-simd)?`), re(`-f(no-)?permissive`), re(`-f(no-)?(pic|PIC|pie|PIE)`), re(`-f(no-)?plt`), re(`-f(no-)?rtti`), re(`-f(no-)?split-stack`), re(`-f(no-)?stack-(.+)`), re(`-f(no-)?strict-aliasing`),
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 20 15:47:34 UTC 2024 - 10K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/a.out.go
REG_F15 REG_F16 REG_F17 REG_F18 REG_F19 REG_F20 REG_F21 REG_F22 REG_F23 REG_F24 REG_F25 REG_F26 REG_F27 REG_F28 REG_F29 REG_F30 REG_F31 // SIMD REG_V0 REG_V1 REG_V2 REG_V3 REG_V4 REG_V5 REG_V6 REG_V7 REG_V8 REG_V9 REG_V10 REG_V11 REG_V12 REG_V13 REG_V14 REG_V15 REG_V16 REG_V17
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 18.1K bytes - Viewed (0) -
src/vendor/golang.org/x/crypto/internal/poly1305/sum_s390x.s
// powers of r that we need from the original equation. // // Notation: // // h - accumulator // r - key // m - message // // [a, b] - SIMD register holding two 64-bit values // [a, b, c, d] - SIMD register holding four 32-bit values // xᵢ[n] - limb n of variable x with bit width i // // Limbs are expressed in little endian order, so for 26-bit
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 17.5K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm64.go
a.Index = num case "D": if !isIndex { return nil } a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_D & 15) << 5) a.Index = num default: return errors.New("unsupported simd register extension type: " + ext) } } else { return errors.New("invalid register and extension combination") } return nil }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Sep 29 09:04:58 UTC 2022 - 10.4K bytes - Viewed (0) -
go.mod
github.com/minio/colorjson v1.0.8 // indirect github.com/minio/filepath v1.0.0 // indirect github.com/minio/mc v0.0.0-20240612143403-e7c9a733c680 // indirect github.com/minio/md5-simd v1.1.2 // indirect github.com/minio/pkg/v2 v2.0.19 // indirect github.com/minio/websocket v1.6.0 // indirect github.com/mitchellh/mapstructure v1.5.0 // indirect
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Thu Jun 13 22:53:53 UTC 2024 - 11.5K bytes - Viewed (0) -
internal/s3select/select.go
} buf.WriteString(s3Select.Output.CSVArgs.RecordDelimiter) return nil case jsonFormat: err := record.WriteJSON(buf) if err != nil { return err } // Trim trailing newline from non-simd output if buf.Bytes()[buf.Len()-1] == '\n' { buf.Truncate(buf.Len() - 1) } buf.WriteString(s3Select.Output.JSONArgs.RecordDelimiter) return nil }
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Fri May 24 23:05:23 UTC 2024 - 21K bytes - Viewed (0) -
src/math/big/arith_arm64.s
//go:build !math_big_pure_go #include "textflag.h" // This file provides fast assembly versions for the elementary // arithmetic operations on vectors implemented in arith.go. // TODO: Consider re-implementing using Advanced SIMD // once the assembler supports those instructions. // func addVV(z, x, y []Word) (c Word) TEXT ·addVV(SB),NOSPLIT,$0 MOVD z_len+8(FP), R0 MOVD x+24(FP), R8 MOVD y+48(FP), R9 MOVD z+0(FP), R10
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 11.8K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go
if regenum >= uint16(B0) && regenum <= uint16(Q31) { if strings.HasPrefix(inst.Op.String(), "F") || strings.HasSuffix(inst.Op.String(), "CVTF") || fOpsWithoutFPrefix[inst.Op] { // FP registers are the same ones as SIMD registers // Print Fn for scalar variant to align with assembler (e.g., FCVT, SCVTF, UCVTF, etc.) return fmt.Sprintf("F%d", regno) } else { // Print Vn to align with assembler (e.g., SHA256H)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 16 22:24:28 UTC 2022 - 17K bytes - Viewed (0) -
src/cmd/internal/obj/link.go
// Encoding: // type = TYPE_REG // reg = REG_[US]XT[BHWX] + register + shift amount // offset = ((reg&31) << 16) | (exttype << 13) | (amount<<10) // // reg.<T> // Register arrangement for ARM64 SIMD register // e.g.: V1.S4, V2.S2, V7.D2, V2.H4, V6.B16 // Encoding: // type = TYPE_REG // reg = REG_ARNG + register + arrangement // // reg.<T>[index] // Register element for ARM64 // Encoding:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 19:57:43 UTC 2024 - 33.1K bytes - Viewed (0)