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Results 1 - 5 of 5 for SIMD (0.06 sec)
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src/vendor/golang.org/x/sys/cpu/cpu.go
HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64) HasSSE3 bool // Streaming SIMD extension 3 HasSSSE3 bool // Supplemental streaming SIMD extension 3 HasSSE41 bool // Streaming SIMD extension 4 and 4.1 HasSSE42 bool // Streaming SIMD extension 4 and 4.2 _ CacheLinePad }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 08 16:12:58 UTC 2024 - 12.1K bytes - Viewed (0) -
src/cmd/go/internal/work/security.go
re(`-fmessage-length=(.+)`), re(`-f(no-)?modules`), re(`-f(no-)?objc-arc`), re(`-f(no-)?objc-nonfragile-abi`), re(`-f(no-)?objc-legacy-dispatch`), re(`-f(no-)?omit-frame-pointer`), re(`-f(no-)?openmp(-simd)?`), re(`-f(no-)?permissive`), re(`-f(no-)?(pic|PIC|pie|PIE)`), re(`-f(no-)?plt`), re(`-f(no-)?rtti`), re(`-f(no-)?split-stack`), re(`-f(no-)?stack-(.+)`), re(`-f(no-)?strict-aliasing`),
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 20 15:47:34 UTC 2024 - 10K bytes - Viewed (0) -
go.mod
github.com/minio/colorjson v1.0.8 // indirect github.com/minio/filepath v1.0.0 // indirect github.com/minio/mc v0.0.0-20240612143403-e7c9a733c680 // indirect github.com/minio/md5-simd v1.1.2 // indirect github.com/minio/pkg/v2 v2.0.19 // indirect github.com/minio/websocket v1.6.0 // indirect github.com/mitchellh/mapstructure v1.5.0 // indirect
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Thu Jun 13 22:53:53 UTC 2024 - 11.5K bytes - Viewed (0) -
internal/s3select/select.go
} buf.WriteString(s3Select.Output.CSVArgs.RecordDelimiter) return nil case jsonFormat: err := record.WriteJSON(buf) if err != nil { return err } // Trim trailing newline from non-simd output if buf.Bytes()[buf.Len()-1] == '\n' { buf.Truncate(buf.Len() - 1) } buf.WriteString(s3Select.Output.JSONArgs.RecordDelimiter) return nil }
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Fri May 24 23:05:23 UTC 2024 - 21K bytes - Viewed (0) -
src/cmd/internal/obj/link.go
// Encoding: // type = TYPE_REG // reg = REG_[US]XT[BHWX] + register + shift amount // offset = ((reg&31) << 16) | (exttype << 13) | (amount<<10) // // reg.<T> // Register arrangement for ARM64 SIMD register // e.g.: V1.S4, V2.S2, V7.D2, V2.H4, V6.B16 // Encoding: // type = TYPE_REG // reg = REG_ARNG + register + arrangement // // reg.<T>[index] // Register element for ARM64 // Encoding:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 19:57:43 UTC 2024 - 33.1K bytes - Viewed (0)