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Results 1 - 10 of 37 for umul (0.06 sec)

  1. src/math/big/float.go

    	}
    
    	// ±0 - y
    	// x - ±Inf
    	return z.Neg(y)
    }
    
    // Mul sets z to the rounded product x*y and returns z.
    // Precision, rounding, and accuracy reporting are as for [Float.Add].
    // Mul panics with [ErrNaN] if one operand is zero and the other
    // operand an infinity. The value of z is undefined in that case.
    func (z *Float) Mul(x, y *Float) *Float {
    	if debugFloat {
    		x.validate()
    		y.validate()
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Jun 06 15:46:54 UTC 2024
    - 44.5K bytes
    - Viewed (0)
  2. src/math/big/arith_arm64.s

    loop:
    	CBZ	R0, done
    	LDP.P	32(R2), (R5, R6)
    	LDP	-16(R2), (R7, R8)
    
    	MUL	R3, R5, R10
    	UMULH	R3, R5, R11
    	ADDS	R4, R10
    	MUL	R3, R6, R12
    	UMULH	R3, R6, R13
    	ADCS	R11, R12
    
    	MUL	R3, R7, R14
    	UMULH	R3, R7, R15
    	ADCS	R13, R14
    	MUL	R3, R8, R16
    	UMULH	R3, R8, R17
    	ADCS	R15, R16
    	ADC	$0, R17, R4
    
    	STP.P	(R10, R12), 32(R1)
    	STP	(R14, R16), -16(R1)
    	SUB	$4, R0
    	B	loop
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:27 UTC 2023
    - 11.8K bytes
    - Viewed (0)
  3. test/codegen/mathbits.go

    }
    
    // --------------- //
    //    bits.Mul*    //
    // --------------- //
    
    func Mul(x, y uint) (hi, lo uint) {
    	// amd64:"MULQ"
    	// arm64:"UMULH","MUL"
    	// ppc64x:"MULHDU","MULLD"
    	// s390x:"MLGR"
    	// mips64: "MULVU"
    	// riscv64:"MULHU","MUL"
    	return bits.Mul(x, y)
    }
    
    func Mul64(x, y uint64) (hi, lo uint64) {
    	// amd64:"MULQ"
    	// arm64:"UMULH","MUL"
    	// ppc64x:"MULHDU","MULLD"
    	// s390x:"MLGR"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 18:51:17 UTC 2024
    - 19.6K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/walk/assign.go

    		ir.OAND,
    		ir.OANDAND,
    		ir.OANDNOT,
    		ir.OBITNOT,
    		ir.OCONV,
    		ir.OCONVIFACE,
    		ir.OCONVNOP,
    		ir.ODIV,
    		ir.ODOT,
    		ir.ODOTTYPE,
    		ir.OLITERAL,
    		ir.OLSH,
    		ir.OMOD,
    		ir.OMUL,
    		ir.ONEG,
    		ir.ONIL,
    		ir.OOR,
    		ir.OOROR,
    		ir.OPAREN,
    		ir.OPLUS,
    		ir.ORSH,
    		ir.OSUB,
    		ir.OXOR:
    		return false
    	}
    
    	// Be conservative.
    	return true
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 08 17:09:06 UTC 2024
    - 20.3K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ir/fmt.go

    	OLE:               "<=",
    	OLSH:              "<<",
    	OLT:               "<",
    	OMAKE:             "make",
    	ONEG:              "-",
    	OMAX:              "max",
    	OMIN:              "min",
    	OMOD:              "%",
    	OMUL:              "*",
    	ONEW:              "new",
    	ONE:               "!=",
    	ONOT:              "!",
    	OOROR:             "||",
    	OOR:               "|",
    	OPANIC:            "panic",
    	OPLUS:             "+",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 05 15:20:28 UTC 2023
    - 26K bytes
    - Viewed (0)
  6. src/crypto/internal/edwards25519/field/fe_test.go

    	x2sq.Square(&x)
    
    	if x2 != x2sq {
    		t.Fatalf("all ones failed\nmul: %x\nsqr: %x\n", x2, x2sq)
    	}
    
    	var bytes [32]byte
    
    	_, err := io.ReadFull(rand.Reader, bytes[:])
    	if err != nil {
    		t.Fatal(err)
    	}
    	x.SetBytes(bytes[:])
    
    	x2.Multiply(&x, &x)
    	x2sq.Square(&x)
    
    	if x2 != x2sq {
    		t.Fatalf("all ones failed\nmul: %x\nsqr: %x\n", x2, x2sq)
    	}
    }
    
    func TestEqual(t *testing.T) {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Aug 28 17:26:17 UTC 2023
    - 13.9K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Select0 m:(LoweredMuluhilo x y)) && m.Uses == 1 => (MULHU x y)
    (Select1 m:(LoweredMuluhilo x y)) && m.Uses == 1 => (MUL x y)
    
    (FADD(S|D) a (FMUL(S|D) x y)) && a.Block.Func.useFMA(v) => (FMADD(S|D) x y a)
    (FSUB(S|D) a (FMUL(S|D) x y)) && a.Block.Func.useFMA(v) => (FNMSUB(S|D) x y a)
    (FSUB(S|D) (FMUL(S|D) x y) a) && a.Block.Func.useFMA(v) => (FMSUB(S|D) x y a)
    
    // Merge negation into fused multiply-add and multiply-subtract.
    //
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  8. test/codegen/arithmetic.go

    	// 386:"SHLL\t[$]5",-"IMULL"
    	// arm:"SLL\t[$]5",-"MUL"
    	// arm64:"LSL\t[$]5",-"MUL"
    	// ppc64x:"SLD\t[$]5",-"MUL"
    	a := n1 * 32
    
    	// amd64:"SHLQ\t[$]6",-"IMULQ"
    	// 386:"SHLL\t[$]6",-"IMULL"
    	// arm:"SLL\t[$]6",-"MUL"
    	// arm64:`NEG\sR[0-9]+<<6,\sR[0-9]+`,-`LSL`,-`MUL`
    	// ppc64x:"SLD\t[$]6","NEG\\sR[0-9]+,\\sR[0-9]+",-"MUL"
    	b := -64 * n2
    
    	return a, b
    }
    
    func Mul_96(n int) int {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 15:28:00 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  9. src/math/pow_s390x.s

    	SLD	$3, R0, R2
    	FMOVD	104(R9), F5
    	WORD	$0xED824004	//ldeb	%f8,4(%r2,%r4)
    	BYTE	$0x00
    	BYTE	$0x04
    	LDEBR	F3, F3
    	FMOVD	96(R9), F6
    	WFMADB	V4, V6, V5, V6
    	FADD	F8, F3
    	WFMADB	V7, V6, V16, V6
    	FMUL	F7, F7
    	FMOVD	88(R9), F5
    	FMADD	F7, F1, F6
    	WFMADB	V4, V5, V3, V16
    	FMOVD	80(R9), F1
    	WFSDB	V16, V3, V3
    	MOVD	$·powtl<>+0(SB), R3
    	WFMADB	V4, V6, V1, V6
    	FMADD	F5, F4, F3
    	FMOVD	72(R9), F1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Jun 14 00:03:57 UTC 2023
    - 16.3K bytes
    - Viewed (0)
  10. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go

    		return true
    	case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC:
    		return true
    	case MODUD, MODSD, MODUW, MODSW:
    		return true
    	case FADD, FADDS, FSUB, FSUBS, FMUL, FMULS, FDIV, FDIVS, FMADD, FMADDS, FMSUB, FMSUBS, FNMADD, FNMADDS, FNMSUB, FNMSUBS, FMULSCC:
    		return true
    	case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC:
    		return true
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 10.9K bytes
    - Viewed (0)
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