Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 4 of 4 for RLWINM (0.21 sec)

  1. test/codegen/shift.go

    	// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
    	f := tab[byte(v)^b]
    	// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
    	f += tab[byte(v)&b]
    	// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
    	f += tab[byte(v)|b]
    	// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
    	f += tab[uint16(v)&h]
    	// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
    	f += tab[uint16(v)^h]
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/ppc64/doc.go

    Examples:
    
    	SRAD $8,R3,R4		=>	sradi r4,r3,8
    	SRD $8,R3,R4		=>	rldicl r4,r3,56,8
    	SLD $8,R3,R4		=>	rldicr r4,r3,8,55
    	SRAW $16,R4,R5		=>	srawi r5,r4,16
    	SRW $40,R4,R5		=>	rlwinm r5,r4,0,0,31
    	SLW $12,R4,R5		=>	rlwinm r5,r4,12,0,19
    
    Some non-simple shifts have operands in the Go assembly which don't map directly
    onto operands in the PPC64 assembly. When an operand in a shift instruction in the
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 21 16:47:45 UTC 2023
    - 11.3K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		{name: "EXTSWSLconst", argLength: 1, reg: gp11, asm: "EXTSWSLI", aux: "Int64"},
    
    		{name: "RLWINM", argLength: 1, reg: gp11, asm: "RLWNM", aux: "Int64"},                           // Rotate and mask by immediate "rlwinm". encodePPC64RotateMask describes aux
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/rewritePPC64latelower.go

    			v.AddArg(n)
    			return true
    		}
    		break
    	}
    	// match: (AND <t> x:(MOVDconst [m]) n)
    	// cond: t.Size() == 4 && isPPC64WordRotateMask(m)
    	// result: (RLWINM [encodePPC64RotateMask(0,m,32)] n)
    	for {
    		t := v.Type
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			x := v_0
    			if x.Op != OpPPC64MOVDconst {
    				continue
    			}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 16.5K bytes
    - Viewed (0)
Back to top