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Results 1 - 5 of 5 for DIVD (0.04 sec)

  1. test/codegen/arithmetic.go

    		// and the normal JMP generated at the end of the block.
    		d += e
    	}
    	return d, e
    }
    
    func NoFix64B(divd int64) (int64, int64) {
    	var d int64
    	var e int64
    	var divr int64 = -1
    	if divd > -9223372036854775808 {
    		d = divd / divr // amd64:-"JMP"
    		e = divd % divr // amd64:-"JMP"
    		d += e
    	}
    	return d, e
    }
    
    func NoFix32A(divr int32) (int32, int32) {
    	var d int32 = 42
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 15:28:00 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/s390x.s

    	MULHDU	R3, R4                // b90400b4b98600a3b904004a
    	MULHDU	R5, R6, R7            // b90400b6b98600a5b904007a
    	MLGR	R1, R2                // b9860021
    	DIVD	R1, R2                // b90400b2b90d00a1b904002b
    	DIVD	R1, R2, R3            // b90400b2b90d00a1b904003b
    	DIVW	R4, R5                // b90400b5b91d00a4b904005b
    	DIVW	R4, R5, R6            // b90400b5b91d00a4b904006b
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 22 03:55:32 UTC 2023
    - 21.6K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    
    		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                // arg0 & arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  4. src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go

    	{VNMLS_EQ_F32, []int{2, 1, 0}, "VNMLS", "NMULSF"},
    	{VNMLS_EQ_F64, []int{2, 1, 0}, "VNMLS", "NMULSD"},
    	{VDIV_EQ_F32, []int{2, 1, 0}, "VDIV", "DIVF"},
    	{VDIV_EQ_F64, []int{2, 1, 0}, "VDIV", "DIVD"},
    	{VNEG_EQ_F32, []int{1, 0}, "VNEG", "NEGF"},
    	{VNEG_EQ_F64, []int{1, 0}, "VNEG", "NEGD"},
    	{VABS_EQ_F32, []int{1, 0}, "VABS", "ABSF"},
    	{VABS_EQ_F64, []int{1, 0}, "VABS", "ABSD"},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 11.9K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		{name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV"},   // arg0/arg1
    		{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS"}, // arg0/arg1
    
    		{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"},   // arg0/arg1 (signed 64-bit)
    		{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"},   // arg0/arg1 (signed 32-bit)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
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