ENOPROTOOPT        = Errno(1109)
	EPROTONOSUPPORT    = Errno(1110)
	ESOCKTNOSUPPORT    = Errno(1111)
	EOPNOTSUPP         = Errno(1112)
	EPFNOSUPPORT       = Errno(1113)
	EAFNOSUPPORT       = Errno(1114)
	EADDRINUSE         = Errno(1115)
	EADDRNOTAVAIL      = Errno(1116)
	ENETDOWN           = Errno(1117)
	ENETUNREACH        = Errno(1118)
	ENETRESET          = Errno(1119)
	ECONNABORTED       = Errno(1120)

		two15, two15 + 3, -3 * two15, -3*two15 + 1,
		two26, two26 + 37, -5 * two26, -5*two26 + 2,
		two34, two34 + 356, -7 * two34, -7*two34 + 13,
		two48, two48 + 3000, -12 * two48, -12*two48 + 1111,
		two57, two57 + 397654, -15 * two57, -15*two57 + 11234,
	}
	for _, x := range xs {
		if int64(int32(x)) == x {
			if want, got := int32(x)%int32(two4) == 0, divisible_int32_2to4(int32(x)); got != want {

	AMRET
	ASRET
	ADRET

	// 3.2.3: Wait for Interrupt
	AWFI

	// 4.2.1: Supervisor Memory-Management Fence Instruction
	ASFENCEVMA

	//
	// RISC-V Bit-Manipulation ISA-extensions (1.0)
	//

	// 1.1: Address Generation Instructions (Zba)
	AADDUW
	ASH1ADD
	ASH1ADDUW
	ASH2ADD
	ASH2ADDUW
	ASH3ADD
	ASH3ADDUW
	ASLLIUW

	// 1.2: Basic Bit Manipulation (Zbb)
	AANDN
	AORN

	// on the second param, verifying the results.
	regRes := configAMD64.ABIAnalyze(ft, false)
	padding := make([]uint64, 32)
	parm := regRes.InParams()[1]
	padding = parm.ComputePadding(padding)
	want := "[1 1 1 0]"
	got := fmt.Sprintf("%+v", padding)
	if got != want {
		t.Errorf("padding mismatch: wanted %q got %q\n", got, want)
	}

	// if r3 is not zero (failed) then branch to finish
	BYTE $0xB9; BYTE $0x02; BYTE $0x00; BYTE $0x33 // lbl1     ltgr  3,3
	BYTE $0xA7; BYTE $0x74; BYTE $0x00; BYTE $0x08 // brc   b'0111',lbl2

	// stomic store shunt address in R5 into CEECAADMC
	BYTE $0xE3; BYTE $0x52; BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x24 // stg   5,0(2)

	FNMADDD	F1, F2, F3, F4				// 4f82201a

	// 12.6: Double-Precision Floating-Point Classify Instruction
	FCLASSD	F0, X5					// d31200e2

	// RISC-V Bit-Manipulation ISA-extensions (1.0)
	// 1.1: Address Generation Instructions (Zba)
	ADDUW		X10, X11, X12			// 3b86a508
	ADDUW		X10, X11			// bb85a508
	SH1ADD		X11, X12, X13			// b326b620
	SH1ADD		X11, X12			// 3326b620
	SH1ADDUW	X12, X13, X14			// 3ba7c620