RewritePatternSet pattern_list(&getContext());
  pattern_list.add<HandleOptionalFrom>(&getContext());
  pattern_list.add<HandleOptionalGet>(&getContext());
  pattern_list.add<HandleOptionalNone>(&getContext());
  pattern_list.add<HandleFunc>(&getContext());
  pattern_list.add<HandleCall>(&getContext());
  pattern_list.add<HandleIf>(&getContext());
  FrozenRewritePatternSet patterns(std::move(pattern_list));

    pass_manager.addNestedPass<mlir::func::FuncOp>(
        mlir::TFL::CreatePostQuantizePass(emit_quant_adaptor_ops));
  }
  pass_manager.addNestedPass<mlir::func::FuncOp>(
      mlir::TFL::CreateOptimizeOpOrderPass());
  // Add optimization pass after quantization for additional fusing
  // opportunities.

  if (!pass_config.unfold_batch_matmul) {
    // Enable an optimization pass that transforms FC to BatchMatmul only when

           << replicate.getN() << ")";
  }

  // add block arg to region. This is in $body.
  unsigned block_arg_idx = replicate.GetNumReplicatedBlockArguments();
  Block& block = replicate.GetBody();
  block_arg = block.insertArgument(block_arg_idx, type, replicate.getLoc());

  // add to $replicated_inputs. This also updates OperandSegmentSizeAttr.

      if (memory_bandwidth >= 0) {
        builder.set_memory_bandwidth(memory_bandwidth);
      }
    }
    // TODO(annarev): Add gflops field in DeviceDescription and set it here.
    // TODO(annarev): Perhaps add `supports_unified_memory` in
    // DeviceDescription.
    return builder.Build();
  }

  absl::StatusOr<std::unique_ptr<Event>> CreateEvent() override {

def CreateTensorScatterNdOp : NativeCodeCall<
    "$_builder.create<TF::ScatterNdOp>($0.getLoc(), $0.getType(), $1, $2, $3)">;

//===----------------------------------------------------------------------===//
// Add op patterns.
//===----------------------------------------------------------------------===//

// We can lower AddOp to AddV2Op, except for string type. AddOp is defined for