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  1. src/cmd/asm/internal/asm/testdata/mips64.s

    //	LAND/LXOR/LOR imm ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	AND	$11, R17, R7	// 3227000b
    	XOR	$341, R1, R23	// 38370155
    	OR	$254, R25, R13	// 372d00fe
    //
    // move immediate: macro for lui+or, addi, addis, and other combinations
    //
    //	LMOVW imm ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVW	$1, R1
    	MOVV	$1, R1
    
    //	LMOVW ximm ',' rreg
    //	{
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
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  2. doc/asm.html

    what the toolchain actually generates for that operation might
    not be a move instruction at all, perhaps a clear or load.
    Or it might correspond exactly to the machine instruction with that name.
    In general, machine-specific operations tend to appear as themselves, while more general concepts like
    memory move and subroutine call and return are more abstract.
    HTML
    - Registered: Tue May 07 11:14:38 GMT 2024
    - Last Modified: Tue Nov 28 19:15:27 GMT 2023
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  3. doc/go_mem.html

    </p>
    
    <p>
    Not introducing data races also means not assuming that loops terminate.
    For example, a compiler must in general not move the accesses to <code>*p</code> or <code>*q</code>
    ahead of the loop in this program:
    </p>
    
    <pre>
    n := 0
    for e := list; e != nil; e = e.next {
    	n++
    }
    i := *p
    *q = 1
    </pre>
    
    <p>
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    - Registered: Tue May 07 11:14:38 GMT 2024
    - Last Modified: Mon Mar 04 15:54:42 GMT 2024
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  4. src/cmd/asm/internal/asm/testdata/riscv64.s

    	FDIVS	F1, F0, F2				// 53011018
    	FMINS	F1, F0, F2				// 53011028
    	FMAXS	F1, F0, F2				// 53111028
    	FSQRTS	F0, F1					// d3000058
    
    	// 11.7: Single-Precision Floating-Point Conversion and Move Instructions
    	FCVTWS	F0, X5					// d31200c0
    	FCVTWS.RNE	F0, X5				// d30200c0
    	FCVTWS.RTZ	F0, X5				// d31200c0
    	FCVTWS.RDN	F0, X5				// d32200c0
    	FCVTWS.RUP	F0, X5				// d33200c0
    	FCVTWS.RMM	F0, X5				// d34200c0
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Mar 22 04:42:21 GMT 2024
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