if symname == nil {
		symname = func(uint64) (string, uint64) { return "", 0 }
	}

	// Adjust opcode [sic].
	switch inst.Op {
	case FDIV, FDIVR, FSUB, FSUBR, FDIVP, FDIVRP, FSUBP, FSUBRP:
		// DC E0, DC F0: libopcodes swaps FSUBR/FSUB and FDIVR/FDIV, at least
		// if you believe the Intel manual is correct (the encoding is irregular as given;
		// libopcodes uses the more regular expected encoding).

			if !isVchar(r) && !isWSP(r) {
				return "", fmt.Errorf("mail: bad character in quoted-string: %q", r)
			}

			qsb = append(qsb, r)
			escaped = false

		case isQtext(r) || isWSP(r):
			// qtext (printable US-ASCII excluding " and \), or
			// FWS (almost; we're ignoring CRLF)
			qsb = append(qsb, r)

		case r == '"':
			break Loop

		case r == '\\':
			escaped = true

		default:

		}
	}

	// Clone should make a copy of bSub, since bSub is just part of b and so is in the arena.
	bSub := b[1:3]
	bSubCopy := UserArenaClone(bSub)
	if unsafe.Pointer(&bSub[0]) == unsafe.Pointer(&bSubCopy[0]) {
		t.Errorf("Clone did not make a copy: %#v -> %#v", bSub, bSubCopy)
	}
	if len(bSub) != len(bSubCopy) {
		t.Errorf("Clone made an incorrect copy (bad length): %d -> %d", len(bSub), len(bSubCopy))
	} else {

			// maintain FP for DUFFCOPY
			q3 := obj.Appendp(q2, c.newprog)
			q3.Pos = p.Pos
			q3.As = ASUB
			q3.From.Type = obj.TYPE_CONST
			q3.From.Offset = 24
			q3.Reg = REGSP
			q3.To.Type = obj.TYPE_REG
			q3.To.Reg = REGFP

			q5 := obj.Appendp(q4, c.newprog)
			q5.Pos = p.Pos
			q5.As = ASUB
			q5.From.Type = obj.TYPE_CONST
			q5.From.Offset = 8
			q5.Reg = REGSP

	OREAL:             "real",
	ORECV:             "<-",
	ORECOVER:          "recover",
	ORETURN:           "return",
	ORSH:              ">>",
	OSELECT:           "select",
	OSEND:             "<-",
	OSUB:              "-",
	OSWITCH:           "switch",
	OUNSAFEADD:        "unsafe.Add",
	OUNSAFESLICE:      "unsafe.Slice",
	OUNSAFESLICEDATA:  "unsafe.SliceData",
	OUNSAFESTRING:     "unsafe.String",

	if a+5 <= 0 {
		return 1
	}

	// arm64:`CMN`,-`ADD`,`(BMI|BPL)`
	if a+13 >= 0 {
		return 2
	}

	// arm64:`CMP|CMN`,-`(ADD|SUB)`,`(BMI|BPL)`
	if a-7 < 0 {
		return 3
	}

	// arm64:`SUB`,`TBZ`
	if a-11 >= 0 {
		return 4
	}

	// arm64:`SUB`,`CMP`,`BGT`
	if a-19 > 0 {
		return 4
	}

	// arm64:`CMNW`,-`ADDW`,`(BMI|BPL)`
	// arm:`CMN`,-`ADD`,`(BMI|BPL)`
	if e+3 < 0 {

			// to be more precise here.
			return len(n.Y.Init()) != 0

		// When using soft-float, these ops might be rewritten to function calls
		// so we ensure they are evaluated first.
		case ir.OADD, ir.OSUB, ir.OMUL, ir.ONEG:
			return ssagen.Arch.SoftFloat && isSoftFloat(n.Type())
		case ir.OLT, ir.OEQ, ir.ONE, ir.OLE, ir.OGE, ir.OGT:
			n := n.(*ir.BinaryExpr)
			return ssagen.Arch.SoftFloat && isSoftFloat(n.X.Type())

	ASLTI
	ASLTIU
	AANDI
	AORI
	AXORI
	ASLLI
	ASRLI
	ASRAI
	ALUI
	AAUIPC
	AADD
	ASLT
	ASLTU
	AAND
	AOR
	AXOR
	ASLL
	ASRL
	ASUB
	ASRA

	// 2.5: Control Transfer Instructions
	AJAL
	AJALR
	ABEQ
	ABNE
	ABLT
	ABLTU
	ABGE
	ABGEU

	// 2.6: Load and Store Instructions
	ALW
	ALWU
	ALH
	ALHU

}

var fpInst []goFPInfo = []goFPInfo{
	{VADD_EQ_F32, []int{2, 1, 0}, "VADD", "ADDF"},
	{VADD_EQ_F64, []int{2, 1, 0}, "VADD", "ADDD"},
	{VSUB_EQ_F32, []int{2, 1, 0}, "VSUB", "SUBF"},
	{VSUB_EQ_F64, []int{2, 1, 0}, "VSUB", "SUBD"},
	{VMUL_EQ_F32, []int{2, 1, 0}, "VMUL", "MULF"},
	{VMUL_EQ_F64, []int{2, 1, 0}, "VMUL", "MULD"},
	{VNMUL_EQ_F32, []int{2, 1, 0}, "VNMUL", "NMULF"},

			return n
		}
		switch n.AsOp {
		case ir.OLSH, ir.ORSH:
			n.X, n.Y, _ = tcShift(n, n.X, n.Y)
		case ir.OADD, ir.OAND, ir.OANDNOT, ir.ODIV, ir.OMOD, ir.OMUL, ir.OOR, ir.OSUB, ir.OXOR:
			n.X, n.Y, _ = tcArith(n, n.AsOp, n.X, n.Y)
		default:
			base.Fatalf("invalid assign op: %v", n.AsOp)
		}
		return n

	// logical operators
	case ir.OANDAND, ir.OOROR: