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Results 1 - 8 of 8 for reg (0.01 sec)

  1. src/archive/tar/testdata/ustar-file-reg.tar

    Joe Tsai <******@****.***> 1443691829 -0700
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Nov 06 04:31:26 UTC 2015
    - 1.5K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/arch/loong64.go

    	}
    
    	if isIndex {
    		arng_type, ok = loong64ElemExtMap[ext]
    		if !ok {
    			return errors.New("Loong64 extension: invalid LSX/LASX arrangement type: " + ext)
    		}
    
    		a.Reg = loong64.REG_ELEM
    		a.Reg += ((reg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT)
    		a.Reg += ((arng_type & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT)
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 05 17:31:25 UTC 2025
    - 3.8K bytes
    - Viewed (0)
  3. src/test/java/jcifs/internal/witness/MockWitnessService.java

            // Count how many registrations this affects
            int affectedRegistrations = 0;
            for (MockRegistration reg : registrations.values()) {
                if (reg.shareName.equalsIgnoreCase(resourceName) || reg.serverAddress.equals(resourceName)) {
                    affectedRegistrations++;
                }
            }
    
    Registered: Sun Sep 07 00:10:21 UTC 2025
    - Last Modified: Sat Aug 23 09:06:40 UTC 2025
    - 8.2K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/lex/lex_test.go

    			"\tb\\",
    			"\tc",
    			"before",
    			"A(1, 2, 3)",
    			"after",
    		),
    		"before.\n.1.\n.2.\n.3.\n.after.\n",
    	},
    	{
    		"LOAD macro",
    		lines(
    			"#define LOAD(off, reg) \\",
    			"\tMOVBLZX	(off*4)(R12),	reg \\",
    			"\tADDB	reg,		DX",
    			"",
    			"LOAD(8, AX)",
    		),
    		"\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n",
    	},
    	{
    		"nested multiline macro",
    		lines(
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 29 07:48:38 UTC 2023
    - 5.8K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/arch/arm.go

    		return true
    	}
    	return false
    }
    
    // IsARMBFX reports whether the op (as defined by an arm.A* constant) is one the
    // BFX-like instructions which are in the form of "op $width, $LSB, (Reg,) Reg".
    func IsARMBFX(op obj.As) bool {
    	switch op {
    	case arm.ABFX, arm.ABFXU, arm.ABFC, arm.ABFI:
    		return true
    	}
    	return false
    }
    
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Oct 23 15:18:14 UTC 2024
    - 6.1K bytes
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  6. src/main/java/jcifs/internal/witness/WitnessRegistration.java

        }
    
        /**
         * Generates a unique registration ID.
         *
         * @return a unique registration identifier
         */
        private String generateRegistrationId() {
            return "REG-" + System.currentTimeMillis() + "-" + Integer.toHexString(System.identityHashCode(this));
        }
    
        /**
         * Gets the next sequence number for this registration.
         *
         * @return the next sequence number
    Registered: Sun Sep 07 00:10:21 UTC 2025
    - Last Modified: Mon Aug 25 14:34:10 UTC 2025
    - 6.7K bytes
    - Viewed (0)
  7. schema/constraint.go

    package schema
    
    import (
    	"regexp"
    	"strings"
    
    	"gorm.io/gorm/clause"
    )
    
    // reg match english letters and midline
    var regEnLetterAndMidline = regexp.MustCompile(`^[\w-]+$`)
    
    type CheckConstraint struct {
    	Name       string
    	Constraint string // length(phone) >= 10
    	*Field
    }
    
    func (chk *CheckConstraint) GetName() string { return chk.Name }
    
    func (chk *CheckConstraint) Build() (sql string, vars []interface{}) {
    Registered: Sun Sep 07 09:35:13 UTC 2025
    - Last Modified: Mon Mar 18 07:33:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/mips.s

    	//	}
    	ABSD	F1, F2
    
    	//	LFADD freg ',' freg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	ADDD	F1, F2
    
    	//	LFADD freg ',' freg ',' freg
    	//	{
    	//		outcode(int($1), &$2, int($4.Reg), &$6);
    	//	}
    	ADDD	F1, F2, F3
    
    	//	LFCMP freg ',' freg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	CMPEQD	F1, F2
    
    
    	//
    	// WORD
    	//
    	WORD	$1
    
    	//
    	// NOP
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 6.7K bytes
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