}

	_, _, ecx1, edx1 := cpuid(1, 0)
	X86.HasSSE2 = isSet(26, edx1)

	X86.HasSSE3 = isSet(0, ecx1)
	X86.HasPCLMULQDQ = isSet(1, ecx1)
	X86.HasSSSE3 = isSet(9, ecx1)
	X86.HasFMA = isSet(12, ecx1)
	X86.HasCX16 = isSet(13, ecx1)
	X86.HasSSE41 = isSet(19, ecx1)
	X86.HasSSE42 = isSet(20, ecx1)
	X86.HasPOPCNT = isSet(23, ecx1)
	X86.HasAES = isSet(25, ecx1)
	X86.HasOSXSAVE = isSet(27, ecx1)
	X86.HasRDRAND = isSet(30, ecx1)

	// CPU features
	hwcap2_DARN = 0x00200000
	hwcap2_SCV  = 0x00100000
)

func osinit() {
	PPC64.IsPOWER8 = isSet(HWCap2, hwcap2_ARCH_2_07)
	PPC64.IsPOWER9 = isSet(HWCap2, hwcap2_ARCH_3_00)
	PPC64.IsPOWER10 = isSet(HWCap2, hwcap2_ARCH_3_1)
	PPC64.HasDARN = isSet(HWCap2, hwcap2_DARN)
	PPC64.HasSCV = isSet(HWCap2, hwcap2_SCV)

	_, ebx7, _, _ := cpuid(7, 0)
	X86.HasBMI1 = isSet(ebx7, cpuid_BMI1)
	X86.HasAVX2 = isSet(ebx7, cpuid_AVX2) && osSupportsAVX
	X86.HasBMI2 = isSet(ebx7, cpuid_BMI2)
	X86.HasERMS = isSet(ebx7, cpuid_ERMS)
	X86.HasADX = isSet(ebx7, cpuid_ADX)
	X86.HasSHA = isSet(ebx7, cpuid_SHA)

	X86.HasAVX512F = isSet(ebx7, cpuid_AVX512F) && osSupportsAVX512
	if X86.HasAVX512F {
		X86.HasAVX512BW = isSet(ebx7, cpuid_AVX512BW)

	ARM.HasTHUMBEE = isSet(hwCap, hwcap_THUMBEE)
	ARM.HasNEON = isSet(hwCap, hwcap_NEON)
	ARM.HasVFPv3 = isSet(hwCap, hwcap_VFPv3)
	ARM.HasVFPv3D16 = isSet(hwCap, hwcap_VFPv3D16)
	ARM.HasTLS = isSet(hwCap, hwcap_TLS)
	ARM.HasVFPv4 = isSet(hwCap, hwcap_VFPv4)
	ARM.HasIDIVA = isSet(hwCap, hwcap_IDIVA)
	ARM.HasIDIVT = isSet(hwCap, hwcap_IDIVT)
	ARM.HasVFPD32 = isSet(hwCap, hwcap_VFPD32)

        if (isSet(mode, 0400)) {
            result.add(OWNER_READ);
        }
        if (isSet(mode, 0200)) {
            result.add(OWNER_WRITE);
        }
        if (isSet(mode, 0100)) {
            result.add(OWNER_EXECUTE);
        }

        if (isSet(mode, 040)) {
            result.add(GROUP_READ);
        }
        if (isSet(mode, 020)) {
            result.add(GROUP_WRITE);

	ARM64.HasASIMDHP = isSet(hwCap, hwcap_ASIMDHP)
	ARM64.HasCPUID = isSet(hwCap, hwcap_CPUID)
	ARM64.HasASIMDRDM = isSet(hwCap, hwcap_ASIMDRDM)
	ARM64.HasJSCVT = isSet(hwCap, hwcap_JSCVT)
	ARM64.HasFCMA = isSet(hwCap, hwcap_FCMA)
	ARM64.HasLRCPC = isSet(hwCap, hwcap_LRCPC)
	ARM64.HasDCPOP = isSet(hwCap, hwcap_DCPOP)
	ARM64.HasSHA3 = isSet(hwCap, hwcap_SHA3)
	ARM64.HasSM3 = isSet(hwCap, hwcap_SM3)
	ARM64.HasSM4 = isSet(hwCap, hwcap_SM4)

	// is not supported in user space on older linux kernels.
	ARM64.HasAES = isSet(HWCap, hwcap_AES)
	ARM64.HasPMULL = isSet(HWCap, hwcap_PMULL)
	ARM64.HasSHA1 = isSet(HWCap, hwcap_SHA1)
	ARM64.HasSHA2 = isSet(HWCap, hwcap_SHA2)
	ARM64.HasCRC32 = isSet(HWCap, hwcap_CRC32)
	ARM64.HasCPUID = isSet(HWCap, hwcap_CPUID)
	ARM64.HasSHA512 = isSet(HWCap, hwcap_SHA512)

	// The Samsung S9+ kernel reports support for atomics, but not all cores

	_PPC_FEATURE2_SCV  = 0x00100000
)

func doinit() {
	// HWCAP2 feature bits
	PPC64.IsPOWER8 = isSet(hwCap2, _PPC_FEATURE2_ARCH_2_07)
	PPC64.IsPOWER9 = isSet(hwCap2, _PPC_FEATURE2_ARCH_3_00)
	PPC64.HasDARN = isSet(hwCap2, _PPC_FEATURE2_DARN)
	PPC64.HasSCV = isSet(hwCap2, _PPC_FEATURE2_SCV)
}

func isSet(hwc uint, value uint) bool {
	return hwc&value != 0

	_SC_IMPL      = 2
	_IMPL_POWER8  = 0x10000
	_IMPL_POWER9  = 0x20000
	_IMPL_POWER10 = 0x40000
)

func osinit() {
	impl := getsystemcfg(_SC_IMPL)
	PPC64.IsPOWER8 = isSet(impl, _IMPL_POWER8)
	PPC64.IsPOWER9 = isSet(impl, _IMPL_POWER9)
	PPC64.IsPOWER10 = isSet(impl, _IMPL_POWER10)
}

// getsystemcfg is defined in runtime/os2_aix.go

}

// Clear removes fd from the set fds.
func (fds *FdSet) Clear(fd int) {
	fds.Bits[fd/NFDBITS] &^= (1 << (uintptr(fd) % NFDBITS))
}

// IsSet returns whether fd is in the set fds.
func (fds *FdSet) IsSet(fd int) bool {
	return fds.Bits[fd/NFDBITS]&(1<<(uintptr(fd)%NFDBITS)) != 0
}

// Zero clears the set fds.
func (fds *FdSet) Zero() {
	for i := range fds.Bits {
		fds.Bits[i] = 0
	}