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Results 1 - 5 of 5 for 1x32x32x16xf32 (0.25 sec)

  1. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_to_nchw.mlir

      %1 = "tf.Transpose"(%arg0, %0) : (tensor<1x3x32x32xf32>, tensor<4xi32>) -> tensor<1x32x32x3xf32>
    
      // Compute in NHWC
      %2 = "tf.Conv2D"(%1, %arg1)
        {
          data_format = "NHWC",
          padding = "SAME",
          strides = [1, 1, 1, 1],
          dilations = [1, 1, 1, 1]
        } : (tensor<1x32x32x3xf32>, tensor<1x1x3x8xf32>) -> tensor<1x32x32x8xf32>
    
      // Convert result back: NHWC -> NCHW
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Mar 24 05:47:26 UTC 2022
    - 1.3K bytes
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  2. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nchw.mlir

             strides = [5, 6, 7, 8]
           } : (tensor<1x32x32x3xf32>, tensor<1x1x3x8xf32>) -> tensor<?x?x?x?xf32>
    
      func.return %0 : tensor<?x?x?x?xf32>
    }
    
    // CHECK-LABEL: func @transposeConv2DBackpropFilter
    func.func @transposeConv2DBackpropFilter(
      %input: tensor<1x32x32x3xf32>,
      %filter_sizes: tensor<4xi32>,
      %out_backprop: tensor<1x32x32x8xf32>
    ) -> tensor<1x1x3x8xf32> {
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 9K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/stablehlo/tests/odml-to-stablehlo-smuggle-resize.mlir

          // CHECK-OPT: %{{.*}} = stablehlo.custom_call @tf.ResizeBilinear(%arg0, %cst) {align_corners = false, device = "", half_pixel_centers = true} : (tensor<1x32x32x128xf32>, tensor<2xi32>) -> tensor<1x64x64x128xf32>
          %1 = "tf.ResizeBilinear"(%arg0, %0) {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sun Apr 14 18:33:43 UTC 2024
    - 1.4K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/lite/tests/get-arithmetic-count.mlir

      func.return %0 : tensor<?x32x32x16xf32>
    }
    
    func.func @testDepthwiseConv2D(tensor<1x112x112x3xf32>, tensor<1x3x3x32xf32>, tensor<32xf32>) -> tensor<1x112x112x32xf32> {
    ^bb0(%arg0: tensor<1x112x112x3xf32>, %arg1: tensor<1x3x3x32xf32>, %arg2: tensor<32xf32>):
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Dec 14 04:58:17 UTC 2022
    - 7.7K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nhwc.mlir

      // CHECK-SAME: dilations = [1, 3, 4, 2]
      // CHECK-SAME: explicit_paddings = [1, 2, 5, 6, 7, 8, 3, 4]
      // CHECK-SAME: padding = "EXPLICIT"
      // CHECK-SAME: strides = [5, 7, 8, 6]
      // CHECK-SAME: (tensor<1x32x32x3xf32>, tensor<1x1x3x8xf32>) -> tensor<1x7x6x8xf32>
    
      // CHECK: %[[RES_PERM:.*]] = "tf.Const"() <{value = dense<[0, 3, 1, 2]> : tensor<4xi64>}>
      // CHECK: %[[RES_TRANSPOSE:[0-9]*]] = "tf.Transpose"(%[[CONV2D]], %[[RES_PERM]])
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 4.5K bytes
    - Viewed (0)
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