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Results 1 - 10 of 19 for 1x256xf32 (1.02 sec)

  1. tensorflow/compiler/mlir/tensorflow/tests/batchmatmul_to_einsum.mlir

      // CHECK-LABEL: test_batch_matmul_adj_to_einsum
      // CHECK: %[[RES_EINSUM:[0-9]*]] = "tf.Einsum"(%arg0, %arg1) <{equation = "...mk,...nk->...mn"}> : (tensor<1x2x3xf32>, tensor<4x3xf32>) -> tensor<1x2x4xf32>
      // CHECK: return %[[RES_EINSUM]] : tensor<1x2x4xf32>
      %0 = "tf.BatchMatMul"(%arg0, %arg1) {adj_x = false, adj_y = true} : (tensor<1x2x3xf32>, tensor<4x3xf32>) -> tensor<1x2x4xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 3K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/quantization/stablehlo/tests/passes/unfuse_mhlo_batch_norm.mlir

    func.func @unfuse_batch_norm(
        %x: tensor<4x256xf32>, %scale: tensor<256xf32>, %offset: tensor<256xf32>,
        %mean: tensor<256xf32>, %variance: tensor<256xf32>)
        -> (tensor<4x256xf32>) {
      // CHECK-DAG: %[[EPS_BCAST:.+]] = mhlo.constant dense<1.001000e-05> : tensor<256xf32>
      // CHECK-DAG: %[[VARIANCE_EPS:.+]] = mhlo.add %[[VARIANCE]], %[[EPS_BCAST]] : tensor<256xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Apr 06 15:32:52 UTC 2024
    - 2.1K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/tests/optimize_batch_matmul.mlir

      %2 = "tfl.batch_matmul"(%1, %arg2) {adj_x = true, adj_y = false, asymmetric_quantize_inputs = false} : (tensor<4x8xf32>, tensor<4x256xf32>) -> tensor<8x256xf32>
      func.return %2 : tensor<8x256xf32>
      // CHECK: return %[[RES1]] : tensor<8x256xf32>
    }
    
    // CHECK-LABEL: Batchmatmul2Fullyconnected
    // CHECK-NOT: "tfl.batch_matmul"
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 9K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_to_nhwc.mlir

           {
             data_format = "NCHW",
             epsilon = 1.001000e-05 : f32
           } : (tensor<?x256x56x56xf32>, tensor<256xf32>, tensor<256xf32>, tensor<256xf32>, tensor<256xf32>)
            -> (tensor<?x256x56x56xf32>, tensor<256xf32>, tensor<256xf32>, tensor<256xf32>, tensor<256xf32>, tensor<*xf32>)
    
      // CHECK: %[[BATCH_NORM1:[_a-z0-9]*]], {{.*}} = "tf.FusedBatchNormV3"
      // CHECK-SAME: %[[CONV1]]
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 7.3K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tensorflow/tests/rewrite_tpu_embedding_ops.mlir

          "tf.Yield"(%0) : (tensor<512x256xf32>) -> ()
        }, {
          "tf.Yield"(%arg2) : (tensor<512x256xf32>) -> ()
        }) { is_stateless = true}: (tensor<i1>) -> tensor<512x256xf32>
        "tf.Yield"(%1) : (tensor<512x256xf32>) -> ()
      }, {
        "tf.Yield"(%arg2) : (tensor<512x256xf32>) -> ()
      }) { is_stateless = true}: (tensor<i1>) -> tensor<512x256xf32>
      func.return %2 : tensor<512x256xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 4.2K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/lite/tests/mlir2flatbuffer/basic_lstm.mlir

    ^bb0(%arg0: tensor<1x384xf32>, %arg1: tensor<1x96xf32>, %arg2: tensor<384x480xf32>, %arg3: tensor<384xf32>, %arg4: tensor<1x96xf32>):
      %0:4 = "tfl.basic_lstm"(%arg0, %arg1, %arg2, %arg3, %arg4) {fused_activation_function = "RELU", cell_clip = 1.0 : f32, proj_clip = 2.0 : f32} : (tensor<1x384xf32>, tensor<1x96xf32>, tensor<384x480xf32>, tensor<384xf32>, tensor<1x96xf32>) -> (tensor<1x96xf32>, tensor<1x96xf32>, tensor<1x480xf32>, tensor<1x384xf32>)
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jul 14 16:41:28 UTC 2022
    - 4.4K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/basic_lstm.mlir

      %0:4 = "tfl.basic_lstm"(%arg0, %arg1, %arg2, %arg3, %arg4) {fused_activation_function = "RELU", cell_clip = 1.0 : f32, proj_clip = 2.0 : f32} : (tensor<1x384xf32>, tensor<1x96xf32>, tensor<384x480xf32>, tensor<384xf32>, tensor<1x96xf32>) -> (tensor<1x96xf32>, tensor<1x96xf32>, tensor<1x480xf32>, tensor<1x384xf32>)
      func.return %0#0 : tensor<1x96xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 1.1K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/tfr/tests/control_flow.mlir

      }
      tfr.return %res : !tfr.tensor
    }
    
    // CHECK-LABEL: pack_one
    func.func @pack_one(%arg0: tensor<2x3xf32>) -> tensor<1x2x3xf32> {
      %0 = "tf.MyPack"(%arg0) {N=1:i32, axis=0:i32} : (tensor<2x3xf32>) -> tensor<1x2x3xf32>
      func.return %0 : tensor<1x2x3xf32>
    
    // CHECK-NEXT: %[[AXIS:.*]] = arith.constant 0 : i32
    // CHECK-NEXT: %[[CAST:.*]] = "tfr.cast"(%arg0) : (tensor<2x3xf32>) -> !tfr.tensor
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Mar 25 10:58:25 UTC 2022
    - 3.2K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/tensorflow/tests/mlir2graphdef/tf_tpu_embedding_ops.mlir

        %0:2 = tf_executor.island wraps "tf.RecvTPUEmbeddingActivations"() {config = "test_config_recv_embedding"} : () -> tensor<512x256xf32> loc("RecvTPUEmbedding")
        %1:1 = tf_executor.island wraps "tf.SendTPUEmbeddingGradients"(%0) {N = 1 : i64, NN = 0 : i64, config = "test_config_send_embedding", operandSegmentSizes = array<i32: 1, 0>} : (tensor<512x256xf32>) -> () loc("SendTPUEmbedding")
        tf_executor.fetch
      }
      func.return
    }
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Aug 14 15:35:49 UTC 2023
    - 1.9K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/lite/stablehlo/tests/unfold_splat_constant_pass.mlir

    func.func @unfold_splat_constant_float() -> tensor<1x750xf32> {
      %cst = mhlo.constant dense<7.680000e+02> : tensor<1x750xf32>
      func.return %cst : tensor<1x750xf32>
    
      // CHECK-DAG: %0 = mhlo.constant dense<7.680000e+02> : tensor<f32>
      // CHECK: %1 = "mhlo.broadcast_in_dim"(%0) <{broadcast_dimensions = dense<> : tensor<0xi64>}> : (tensor<f32>) -> tensor<1x750xf32>
      // CHECK: return %1 : tensor<1x750xf32>
    }
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Apr 06 15:32:52 UTC 2024
    - 1.3K bytes
    - Viewed (0)
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